Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-23
2002-10-22
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S253000
Reexamination Certificate
active
06469336
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the formation of contacts in integrated circuits, and more particularly to a method of forming bit line contacts in dynamic random access memory chips.
BACKGROUND OF THE INVENTION
Integrated circuits, also commonly referred to as semiconductor devices, are formed of various electrically conducting, semiconducting and insulating materials. Silicon, in single crystal, amorphous or polycrystalline form, is the most commonly used semiconductor material. Silicon can be made electrically conductive by adding impurities, commonly referred to as doping. Through a series of doping, deposition and etch steps, electrical devices are formed and interconnected to produce the integrated circuits.
Dynamic random access memory (DRAM) circuits include arrays of memory cells, each of which includes two basic components: a field effect transistor (FET) and a storage capacitor. Typically, a semiconducting substrate is doped to produce active areas of an access transistor, one of which is connected to the lower or storage electrode of the capacitor. The other active area and the transistor gate electrode are connected to external connection lines, namely digit or bit lines and word lines or rows. The top or reference electrode of the capacitor is connected to a reference voltage. DRAM arrays thus include a transistors, capacitors and contacts to interconnecting lines.
It is advantageous to form integrated circuits with smaller individual elements so that as many elements as possible may be formed in a single chip. In this way, electronic equipment becomes smaller and more reliable, assembly and packaging costs are minimized and circuit performance is improved. In particular, denser device packing leads to faster and more efficient circuit operation. Despite the focus on continued miniaturization, the storage capacity of the cell capacitor must generally remain above a minimum level to ensure reliable operation (low error rates). Consequently, the development of faster and more powerful DRAM chips focuses in large part on maintaining capacitance despite shrinking available chip area for each memory cell.
One way in which capacitance has been increased has been to increase the surface area of the capacitor electrodes by creating three-dimensional folding structures to which the electrodes conform. When the capacitor is formed above the transistors, they are known in the industry as “stacked” capacitors. Stacked capacitors advantageously demonstrate high capacitance per unit of occupied chip area (“footprint”), high reliability and simple process integration relative to other capacitor designs.
As noted, in the process of fabricating a DRAM chip, electrical connections must be made to the transistor active areas. The active areas, which are also known as source and drain regions, are discrete doped regions in the surface of the semiconductor substrate. As the size of the DRAM is reduced, the size of the active areas and the corridors available for contacts to reach the active areas are also reduced. At the same time, insulating materials must be maintained to effectively isolate the contacts from the transistor and capacitor components. Accordingly, the width of bit line contacts, and other integrated contacts generally, must shrink as device packing density increases.
Unfortunately, while contact width continually decreases, contact height cannot decrease proportionately. Rather, the contact height is defined by the thickness of the interlevel dielectric (ILD) which separates the two levels in the circuit, such as the substrate and higher wiring levels. The ILD thickness, in turn, must be maintained to minimize the risk of short circuits, as well as to prevent interlevel capacitance, which can tie up electrical carriers and slow signal propagation.
Relative increases in contact height is particularly acute in DRAM circuit designs which incorporate stacked capacitors. As noted, capacitance is proportional to the surface area, which depends on both height and width. In order to maintain the same or higher level of capacitance from generation to generation, the capacitor height must remain the same or even increase as device spacing decreases. In bit-over-capacitor (BOC) designs, the bit line contact increases in height along with the capacitor.
While contact width decreases and contact height is essentially maintained, the aspect ratio (defined as the ratio of height to width of a contact) of contacts continues to increase. In general, therefore, each successive generation of integrated circuits contacts of higher aspect ratios, and this is particularly true for certain DRAM circuit designs. As is well known in the art of integrated circuit fabrication, high aspect ratio contact vias are very difficult to fill without forming keyholes.
One partial solution to this problem is to reduce the dielectric constant of the ILD. A lowered dielectric constant enables thinning ILDs for a given tolerable parasitic capacitance, and consequently lowers the aspect ratio. This solution, however, can only be carried so far before the dielectric loses its insulating qualities, or the risk of short circuits through the thinned ILD becomes too high. Moreover, this solution does not address the high aspect ratios of bit line contacts necessitated by high stacked capacitors in bit-over-capacitor DRAM circuit designs.
Accordingly, a need exists for more effective methods of forming contacts between levels in integrated circuits.
SUMMARY OF THE INVENTION
In accordance with a disclosed embodiment, intermediate conductive plugs raise the platform from which a contact extends. In DRAM fabrication, for example, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug.
In one embodiment, sacrificial plugs are simultaneously formed adjacent the intermediate metal plugs. The sacrificial plugs can be selectively removed, while the intermediate plugs are shielded from etch, and the capacitors formed in the resulting container. In another embodiment, the bottom electrodes for stud capacitors are simultaneously formed adjacent the intermediate metal plugs.
In accordance with one aspect of the invention, therefore, an integrated circuit contact is provided. The integrated circuit includes an electronic device formed above a semiconductor substrate, extending from a first level to a second level. A conducting line overlies the electronic device, electrically insulated by an interlevel dielectric. A contact plug extends downwardly through the interlevel dielectric to an intermediate level above the first level, while remaining electrically insulated from the direct contact with the electronic device.
In accordance with another aspect of the invention, a method is provided for forming electrical contact between levels in an integrated circuit. A conductive plug is formed and covered with a shield. While the plug remains covered, an electrical device is at least partially formed adjacent the conductive plug. After the shield is opened, a contact is then extended to directly contact the conductive plug.
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Sakao et al., “A Capacitor-
Agarwal Vishnu K.
Deboer Scott J.
Knobbe Martens Olson & Bear LLP
Le Dung A
Micro)n Technology, Inc.
Nelms David
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