Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-03
2002-10-22
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S506000
Reexamination Certificate
active
06469338
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and manufacturing method thereof. More specifically, the present invention relates to a structure of an EEPROM (Electrically Erasable and Programmable Read Only Memory) and manufacturing method thereof.
2. Description of the Background Art
Conventionally, an EEPROM which allows programming of data freely and allows electrical writing and erasing of information has been known as one of the non-volatile semiconductor memory devices. The EEPROM has a source region, a drain region and a control gate electrode. These are arranged in various manners. An EEROM has been known in which an impurity region extending in one direction provided at the surface of a semiconductor substrate is used as the source and drain regions for miniaturization.
The structure of such an EEPROM will be described in the following.
FIG. 29
is a cross section of the EEPROM described in Japanese Patent Laying-Open No. 8-107158. Referring to
FIG. 29
, a memory cell transistor
500
constituting the EEPROM includes an Si substrate
511
, a source region
515
a
, a drain region
515
b
, polycrystalline Si films
521
a
,
521
b
and a silicide film
526
b
as the floating gate electrode, and a polycrystalline Si film
523
as a control gate electrode.
Source and drain regions
515
a
and
515
b
formed in Si substrate
511
are formed to extend from this side to the depth side of the sheet. Control gate electrode
523
extends from the right to the left direction of
FIG. 29
, that is, in the direction crossing the direction of extension of the source and drain regions
515
a
and
515
b.
An SiO
2
film
514
in a pattern of element isolating region is formed on Si substrate
511
. An SiO
2
film
517
as a gate oxide film is formed on the surface of Si substrate
511
. Polycrystalline Si film
521
a
constituting the floating gate electrode is formed on SiO
2
film
517
. Silicide film
526
b
is formed on polycrystalline Si film
521
a.
Silicide film
526
a
is formed on the surfaces of source and drain regions
515
a
and
515
b .
An SiO
2
film
525
is formed on a sidewall of polycrystalline Si film
521
a
. On Si substrate
511
, an interlayer insulating film
527
is formed. Polycrystalline Si film
521
b
constituting the floating gate electrode is formed on interlayer insulating film
527
. An ONO film
522
including a stack of an oxide film, a nitride film and an oxide film is formed on polycrystalline Si film
521
b
. Polycrystalline Si film
523
as the control gate electrode is formed on ONO film
522
.
In such an EEPROM, source and drain regions
515
a
and
515
b
are formed by impurity regions extending in one direction at the surface of Si substrate
511
. Therefore, the number of interconnection layers can be reduced as compared with such EEPROMs in which the source and drain regions are formed in the shape of islands which are connected by interconnection layers. Therefore, the EEPROM of the above described type is suitable for miniaturization. IEDM86, pp. 592 to 595 describes an EPROM (Electrically Programmable Read Only Memory) in which impurity regions extending in one direction are used as source and drain regions.
In such an EEPROM as shown in
FIG. 29
, presence/absence of information (data) is determined dependent on whether electrons are stored or not in the floating gate electrode constituted by polycrystalline Si film
521
a
,
521
b
and silicide film
526
b.
When electrons are injected in the floating gate electrode, the threshold voltage of memory cell transistor
500
assumes a high value of Vthp. This state is referred to as a programmed state. In this state, data “0” is stored in memory cell transistor
500
.
The electrons accumulated in the floating gate electrode do not dissipate but are kept semi-permanently, and therefore the stored data is held semi-permanently.
When electrons are not accumulated in the floating gate electrode, the threshold value of memory cell transistor
500
attains to a low value of Vthe. This state is referred to as an erased state. In this state, data “1” is stored in memory cell transistor
500
. By detecting these two states, data stored in memory cell transistor
500
can be read.
The operation of memory cell transistor
500
shown in
FIG. 29
will be described.
At the time of programming, a positive high voltage Vpp (typically about 20V) is applied to control gate electrode
523
. Si substrate
511
, source region
515
a
and drain region
515
b
are set to the ground potential. Accordingly, electrons gather in the channel region formed between the source and drain regions
515
a
and
515
b
, which electrons are injected to the floating gate electrode by tunneling phenomenon. As a result, the threshold voltage of memory cell transistor
500
attains higher to Vthp.
Among memory cell transistors not selected at the time of programming, in that one which shares control gate electrode
523
with memory cell transistor
500
, a high voltage of about 20V is applied to control gate electrode
523
, a voltage of about 7 volt is applied to the drain region, the source region is set to the floating state and the substrate is set to the ground potential.
At the time of erasure, a negative high voltage Vpp (typically about −20V) is applied to control gate electrode
523
, and source region
515
a
, drain region
515
b
and Si substrate
512
are set to the ground potential. Accordingly, the electrons which have been stored in the floating gate electrode are discharging by the tunneling phenomenon to Si substrate
511
. As a result, the threshold voltage of memory cell transistor
500
lowers to Vthe.
In a reading operation of selected memory cell transistor
500
, assuming that Vthe<3.3V<Vthp, 3.3V is applied to control gate electrode
523
and drain region
515
b
. Source region
515
a
and Si substrate
511
are set to the ground potential.
The threshold voltage Vthp in the programmed state is higher than 3.3V, and therefore in the programmed state, no current flows between the source and drain regions
515
a
and
515
b
. As the threshold voltage Vthp in the erased state is smaller than 3.3V, current flows between source and drain regions
515
a
and
515
b
in the erased state.
At the time of reading, in the non-selected memory cell transistor, the control gate electrode is set to the ground potential, 3.3V is applied to the drain region, and the source region and the Si substrate are set to the ground potential. At this time, since the threshold voltages Vthp and Vthe are generally larger than 0V, no current flows between the source and drain regions of the memory cell transistor if the voltage applied to the control gate electrode is 0V.
In the above described memory cell transistor, during the process of heating for forming SiO
2
film
514
on Si substrate
511
, SiO
2
film
514
tends to extend in the direction of the longer side. Thereafter, SiO
2
film
514
is cooled and tends to contract in the longer side direction.
In the step of thermal diffusion for forming source and drain regions
515
a
and
515
b
, the source and drain regions
515
a
and
515
b
tend to extend in the direction of the longer side. Thereafter, the source and drain regions
515
a
and
515
b
tend to contract in the direction of the longer side. This causes tensile or compressive stress to Si substrate
511
. Accordingly, crystal defect results in the channel region between the source and drain regions
515
a
and
515
b
. A crystal defect tends to occur when stress remains in the <110> direction. Since arsenic which is implanted in the source or drain region
515
a
or
515
b
is trapped in the crystal defect, the distance (channel length) between the source and drain regions
515
a
and
515
b
is made shorter. When such a memory cell transistor is selected and the voltage of 3.3V is applied to the drain region
515
b
, a current always flows because of punch through between the source and drain regions
515
a
and
Kobayashi Kiyoteru
Tsuji Naoki
Chaudhuri Olik
Mitsubishi Denki & Kabushiki Kaisha
Peralta Ginette
LandOfFree
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