Semiconductor memory device having redundancy function

Details Semiconductor memory device having redundancy function Semiconductor memory device having redundancy function

2001-09-05

2002-10-01

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S149000, C365S051000, C365S063000, C257S296000, C438S241000

Reexamination Certificate

active

06459632

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically to a semiconductor memory device provided with a spare memory cell for replacing a defective normal memory cell.
2. Description of the Background Art
A conventional DRAM (Dynamic Random Access Memory; hereinafter referred to as a semiconductor memory device) will be described with reference to FIG.
10
. As can be seen from
FIG. 10
, a conventional semiconductor memory device
9000
includes a plurality of normal memory cells arranged in a matrix of rows and columns, a plurality of normal word lines
91
#
1
to
91
#
4
corresponding to the rows, a plurality of bit lines
93
#
1
to
93
#
4
corresponding to the columns, spare word lines
92
#
1
to
92
#
2
which can replace normal word lines, and a plurality of spare memory cells for replacing defective normal memory cells.
The normal word line and the spare word line are connected to a row decoder
80
, and set to a selected state in accordance with a row address input to an external address input terminal (not shown). Row decoder
80
includes redundancy circuit for selecting, when an input row address corresponds to defective address, a spare word line corresponding to the defective address.
Bit lines
93
#
1
and
93
#
2
are connected to a sense amplifier
82
#
1
, and bit lines
93
#
3
and
93
#
4
are connected to a sense amplifier
82
#
2
. Sense amplifiers
82
#
1
and
82
#
2
are connected to a column decoder
84
, and set to a selected state in accordance with a column address input to an external address input terminal (not shown).
Reference characters
94
#
1
to
94
#
8
of
FIG. 10
represent storage nodes of capacitors included in normal memory cells, and reference characters
99
#
1
to
99
#
4
represent storage nodes of capacitors included in spare memory cells. Reference numeral
95
denotes a source/drain region. For example, a memory cell including storage node
94
#
1
is selected by normal word line
91
#
3
. Thus, stored charges are transmitted through a bit line contact
98
to bit line
93
#
1
.
In such a structure, when the normal memory cell including storage node
94
#
1
is defective and an activating signal for selecting normal word line
91
#
3
is generated, row decoder
80
operates not to activate the normal word line but to activate spare word line
92
#
1
. Accordingly, charges of the spare memory cell are transmitted to bit line
93
#
2
. Sense amplifier
82
#
1
amplifies charges of the spare memory cell including storage node
99
#
1
, instead of the normal memory cell including storage node
94
#
1
. More specifically, normal word line
91
#
3
is replaced by spare word line
92
#
1
, whereby the normal memory cell connected to normal word line
9
1
#
3
is replaced by spare word line
92
#
1
, whereby the normal memory cell connected to normal word line
91
#
3
is replaced by spare memory cell connected to spare word line
92
#
1
.
In the conventional semiconductor memory device, the normal word lines and spare word lines are the same structure, and normal memory cells and spare memory cells are manufactured to have the same size.
Therefore, normal memory cells as well as spare memory cells may possibly be defective.
When the spare memory cell does not normally function because of the defect, however, a defective normal memory cell, if any, cannot be repaired. Therefore, it is desired that the possibility of defects in the spare memory cell is lower than in the normal memory cell.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device in which possibility of defect in the spare memory cell is reduced, for ensuring repairment.
According to an aspect of the present invention, the semiconductor memory device includes a plurality of normal memory cells arranged in a matrix of rows and columns, a plurality of normal word lines provided corresponding to the rows of the plurality of normal memory cells, a plurality of spare memory cells arranged in a matrix of rows and columns for replacing a defective normal memory cell among said plurality of normal memory cells, and a plurality of spare word lines provided corresponding to the rows of the plurality of spare memory cells, wherein the spare word lines are respectively arranged such that minimum space between the spare word lines is made wider than minimum space between the plurality of normal word lines.
Preferably, the plurality of spare word lines are respectively arranged such that minimum space between the plurality of spare word lines and the plurality of normal word lines is wider than minimum space between the plurality of normal word lines.
Preferably, the plurality of normal memory cells each include a first memory cell capacitor and a first memory cell transistor which is rendered conductive by the corresponding normal word line, and the plurality of spare memory cells each include a second memory cell capacitor having larger capacitance than the capacitance of the first memory cell capacitor, and a second memory cell transistor which is rendered conductive by the corresponding spare word line.
Preferably, the plurality of spare memory cells are arranged such that minimum distance between the plurality of spare memory cells and the plurality of normal memory cells is longer than minimum distance between the plurality of normal memory cells.
Preferably, the plurality of spare memory cells are arranged such that minimum distance between the plurality of spare memory cells is longer than minimum distance between the plurality of normal memory cells.
Therefore, in the semiconductor memory device described above, the space between the spare word lines is made wider than the space between the normal word lines, so that the possibility of contact defect caused by a foreign matter between spare word lines can be reduced. Therefore, it becomes possible to surely repair the defective normal memory cell and to improve production yield of the semiconductor memory device.
Further, as the space between a normal word line and a spare word line is made wider than the space between normal word lines, possibility of contact defect caused by a foreign matter between the normal word line and the spare word line can be reduced.
As the storage nodes in the spare memory cells are widened, pause refresh characteristic of the spare memory cell can be improved. Further, as the distance between a normal memory cell and a spare memory cell is made longer than the distance between normal memory cells, possibility of contact defect caused by a foreign matter between the normal memory cell and the spare memory cell can be reduced.
Further, as the distance between spare memory cells is made longer than the distance between normal memory cells, possibility of contact defect caused by a foreign matter between spare memory cells can be reduced.
According to another aspect of the present invention, the semiconductor memory device includes a memory cell forming region in which a plurality of normal memory cells arranged in a matrix of rows and columns and a plurality of spare memory cells for replacing a defective normal memory cell among the plurality of normal memory cells are formed, and a dummy forming region formed at an outermost periphery of the memory cell forming region, wherein the plurality of normal memory cells each include a first memory cell transistor and a first memory cell capacitor, and the plurality of spare memory cells each include a second memory cell transistor and a second memory cell capacitor having larger capacitance than the first memory cell capacitor, formed to extend to the dummy forming region.
Preferably, the dummy forming region includes a region where a dummy cell is formed and a region where a- dummy interconnection is formed, and the second memory cell capacitor includes a storage node extending in a dir

Affiliated with

Also associated with

Rating

Semiconductor memory device having redundancy function does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having redundancy function, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having redundancy function will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2987899