Memory system for synchronized and high speed data transfer

Details Memory system for synchronized and high speed data transfer Memory system for synchronized and high speed data transfer

1999-04-02

2002-11-12

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S170000, C713S400000, C713S503000, C713S401000

Reexamination Certificate

active

06480946

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory system and, more specifically, to such a memory system that a plurality of discrete memory devices connected parallel to a bus transmit/receive signals to and from a commonly provided controller. More specifically, the present invention relates to a memory system in which the plurality of discrete memory devices are memory devices operating in synchronization with a clock signal.
2. Description of the Background Art
FIG. 56
shows an example of a conventional memory system configuration. In
FIG. 56
, a plurality of discrete memory devices (memory chips) CH#
0
to CH#n are arranged in parallel. A clock signal line CKBS for transmitting a clock signal CLK from a clock driver CKD, a command/address bus CDBS for transmitting an address and a command for designating an operation mode, and a data bus DTBS for transferring data DQ are provided common to the memory chips CH#
0
to CH#n. The clock signal line CKBS, the command/address bus CDBS and the data bus DTBS are coupled to a memory controller MC controlling operations of memory chips CH#
0
to CH#n.
Memory controller MC transmits a command designating an operation mode and an address on command/address bus CDBS in synchronization with clock signal CLK on clock signal line CKBS. Each of the memory chips CH#
0
to CH#n take in the command and address signals applied on command/address bus CDBS in synchronization with clock signal CLK, to perform the designated operation. Data bus DTBS is a bi-directional data bus and the data bus transmits write data from memory controller MC to memory chips CH#
0
to CH#n at the time of data write and, transmits data read from memory chips CH#
0
to CH#n to memory controller MC at the time of data read.
As it is possible to transfer data in synchronization with clock signal CLK, data transfer at high speed is realized. Further, as the plurality of memory chips CH#
0
to CH#n are provided in parallel, a memory system having large storage capacity can be implemented.
A memory chip for such a memory system may include a synchronous dynamic random access memory (SDRAM), a SYNCLINK DRAM (SLDRAM) and a Rambus DRAM (RDRAM)).
In a memory system using these clock synchronous memories, every data bus DTBS is a bi-directional data bus, and write data D and read data Q are both transferred through data bus DTBS.
In a conventional memory system, time of arrival of data DQ transmitted through data bus DTBS at memory controller MC differs among memory chips CH#
0
to CH#n. In order to realize accurate data transmission/reception between memory controller MC and each of the memory chips CH#
0
to CH#n, a clock signal (DCLK or QS) used for taking data only is utilized (DDR SDRAM (double data rate SDRAM), an SLDRAM, a direct RDRAM and so on).
At the time of data write, memory controller MC transmits both the write data and a data write strobe clock signal providing a timing for taking the write data. At the time of data read, memory chips CH#
0
to CH#n transmit the read data and a clock signal (QS) for data taking together to memory controller MC. Therefore, as data and the clock signal providing the timing for data taking are transmitted over the same distance, there is only a little skew between the clock signal and the data, and hence data can be taken in at a relatively accurate timing.
In the conventional memory system, however, taking of the command designating an operation mode and the address signal is performed simply in synchronization with the clock signal CLK with no consideration at all of the skew (derived from line resistance and line capacitance) between the clock signal CLK and the command/address. Therefore, it is necessary that memory chips CH#
0
to CH#n start up internal operation taking into account a margin for the skew between the clock signal and the command or address, which necessity hinders high speed access.
Further, the distance between memory chip CH#
0
and memory controller MC is the shortest while the distance between memory chip CH#n and memory controller MC is the longest. Thus, time of data transfer between memory chip CH#
0
and memory controller MC is the shortest, while the time of data transfer between memory chip CH#n and memory controller MC is the longest. In order to eliminate difference among time periods of signal propagation from memory chips CH#
0
to CH#n (signal flight time), the number of memory chips CH#
0
to CH#n may be made as small as possible to shorten the length of data bus DTBS. In that case, however, the number of memory chips contained in the memory system is limited, making it difficult to provide a memory system having large strange capacity.
Let us consider an approach in which flight times of data when data are read from memory chips CH#
0
to CH#n are made equal, so that memory chips CH#
0
to CH#n come to have the same response to a command. Here, it becomes necessary to make longer the latency of memory chip CH#
0
and to make shorter the latency of memory chip CH#n. Here, the latency refers to the number of clock cycles necessary from an application of a read command until valid data is output to data bus DTBS. Therefore, in this case, it is necessary for memory chips closer to memory controller MC to have the latency longer than necessary, which means that performance of memory chips closer to memory controller MC is degraded.
When read data Q and write data D are to be transmitted through bi-directional data bus DTBS, it is necessary that read data Q arrives at memory controller MC and thereafter write data D is transmitted to bi-directional data bus DTBS. Therefore, if the data bus DTBS is long and data is to be read from the farthest memory chip CH#n, the write data cannot be transmitted to data bus DTBS until after the read data arrives at memory controller MC. This lowers efficiency in use of data bus DTBS, hindering implementation of a high speed memory system. In a data write, it is necessary to read data while preventing collision with the write data, taking into account the time period necessary for the write data to arrive at the farthest memory chip CH#n, which similarly lowers the efficiency in use of the data bus DTBS.
SUMMARY OF THE INVENTION
A object of the present invention is to provide a memory system which significantly improves efficiency in use of the. data bus.
Another object of the present invention is to provide a memory system capable of efficient data transfer without unnecessarily degrading performance of the memory chip.
A further object of the present invention is to provide a memory system capable of accurate transmission/reception of signals including data between memory chips and a controller, regardless of the distance between the controller and the memory chips.
In accordance with a first aspect, the memory system includes a first signal bus arranged between a first port and a second port arranged opposing to the first port, coupled to the first and second ports, for transmitting signals including data in one direction from the first port to the second port, and a plurality of first individual memory devices coupled to the first signal bus in parallel with each other, for communicating signals with the first signal bus.
According to the second aspect, the memory system includes a plurality of individual memory devices arranged on a first surface of a base board, a line disposed electrically continuous over the first surface and a second surface opposing to the first surface of the base board, to which the plurality of individual memory devices are coupled in common, and a control unit coupled in common to the plurality of individual memory devices through the line for transmitting and receiving signals to and from the plurality of individual memory devices through the line. Along one direction of the line, the sum of a line length from the control unit to one indi

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