Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-09-01
2002-11-05
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S233500, C365S230040, C365S225700, C365S194000
Reexamination Certificate
active
06477107
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly to integrated circuit memory devices and methods of operating integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Computer systems typically include a central processing unit (CPU) for performing commands and a main memory for storing data and programs required by the CPU. Thus, increasing the operational speed of the CPU and reducing the access time of the main memory can enhance the performance of the computer system. As will be understood by those skilled in the art, a synchronous DRAM (SDRAM) operates according to control of a system clock and typically provides a short access time when used as a main memory.
In particular, the operation of the SDRAM is controlled in response to pulse signals generated by transitions of a system clock. Here, the pulse signals are generated during a single data rate SDR mode or a dual data rate DDR mode. The SDR mode generates pulse signals with respect to transitions in one direction (e.g., pulse signals of ‘high’ to ‘low’ or vice versa) to operate a DRAM device. However, the DDR mode generates pulse signals with respect to transitions in both directions (e.g., pulse signals of ‘high’ to ‘low’ and vice versa) to operate the DRAM device.
The DDR mode enables a memory device to have wide bandwidth operation. Thus, the DDR mode is very helpful when making an ultra-high speed SDRAM. However, to implement the DDR mode, the layout area of the memory device typically must be increased because twice as many data lines may need to be provided. Also, in the DDR mode compared with the SDR mode, set-up time and data hold time between data and the clock during reading and writing are reduced, so that auxiliary circuits (e.g., phase locked loops (PLL) or delay locked loops (DLL)) for delaying an external clock are often necessary. This requirement may lead to further increase in the size of the memory chip. Therefore, only memory devices for ultra-high speed systems typically utilize the DDR mode, whereas other memory devices typically utilize the SDR mode.
Notwithstanding these known aspects of conventional memory devices, there continues to exist a need for improved memory devices and methods of operating same.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved integrated circuit memory devices and methods of operating same.
It is another object of the present invention to provide integrated circuit memory devices having dual and single data rate modes of operation and methods of operating same.
These and other objects, advantages and features of the present invention are provided by integrated circuit memory devices which include first and second memory banks, first and second local data lines electrically coupled to the first and second memory banks, respectively, and a multiplexer having first and second inputs electrically coupled to first and second data bus lines, respectively. A data selection circuit is also provided which routes data from the first and second local data lines to the first and second data bus lines, respectively, when a selection control signal is in a first logic state and routes data from the second and first local data lines to the first and second data bus lines, respectively, when a selection control signal is in a second logic state opposite the first logic state. A control signal generator is also provided. This control signal generator generates the selection control signal in the first and second logic states when a first address in a string of burst addresses is even and odd, respectively.
According to a preferred aspect of the present invention, the data selection circuit includes a first sense amplifier having an input electrically coupled to the first local data line, a second sense amplifier having an input electrically coupled to the second local data line, a first selector having a first input electrically coupled to an output of the first sense amplifier and a second input electrically coupled to an output of the second sense amplifier. A second selector is also provided which has a first input electrically coupled to the output of the first sense amplifier and a second input electrically coupled to the output of the second sense amplifier.
According to another aspect of the present invention, the first and second sense amplifiers are both responsive to a first control signal, the first and second selectors are responsive to second and third control signals, respectively, and the multiplexer is responsive to fourth and fifth control signals. The second and third control signals are in-sync with opposite edge transitions of an internal clock signal and the fourth and fifth control signals are preferably delayed versions of the second and third control signals, respectively. Thus, the timing of the internal clock signal can be used to control the timing of data transfer. A data rate mode control signal can also be used to control the timing of the internal clock signal relative to a system clock and thereby provide multiple data rate mode capability.
REFERENCES:
patent: 4758995 (1988-07-01), Sato
patent: 5844859 (1998-12-01), Iwamoto et al.
patent: 5892730 (1999-04-01), Sato et al.
patent: 6014759 (2000-01-01), Manning
patent: 6151271 (2000-11-01), Lee
Saeki et al., “SP23.4: A 2.5ns Clock Access 250MHz 256Mb SDRAM With a Synchronous Mirror Delay”, ISSCC, 1996, pp. 374-375.
Elms Richard
Myers Bigel & Sibley & Sajovec
Nguyen Tuan T.
Samsung Electronics Co,. Ltd.
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