Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-09-13
2002-12-17
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06496972
ABSTRACT:
FIELD OF THE INVENTION
The field of the present invention pertains to the field of integrated circuit design optimization using electronic design automation tools. More particularly, aspects of the present invention pertain to a circuit design optimization process for use in the design of complex integrated circuits with computer aided design (CAD) tools.
BACKGROUND OF THE INVENTION
Computer systems, software applications, and the devices and processes built around them are continually growing in power and complexity. Society's reliance on such systems is likewise increasing, making it critical that the systems deliver the expected performance and obey the properties that their designers intended. As each successive generation of computer and software implemented systems and processes become more powerful, the task of designing and fabricating them becomes increasingly difficult.
The design and manufacture of increasingly complex integrated circuits involves extensive use of CAD tools. The development of ASICs (application specific integrated circuits) and other complex integrated circuits using CAD tools is referred to as electronic design automation, or EDA. The design, checking, and testing of large-scale integrated circuits are so complex that the extensive use of CAD and EDA tools are required for realization of modern, complex integrated circuits.
The development of a new integrated circuit device begins with a design phase involving extensive use of CAD tools to facilitate various aspects of designing the new integrated circuit device. Typically, CAD tools function in part by decomposing the overall desired behavior of the integrated circuit into simpler functions which are more easily manipulated and processed by the CAD tool. The CAD tool performs considerable computation to generate an efficient layout of a resulting “network” of design elements (e.g., logic gates, storage elements, etc.). The resulting network, commonly referred to as a netlist, comprises a detailed specification defining the integrated circuit, typically in terms of a particular fabrication technology (e.g., CMOS). The netlist can be regarded as a template for the fabrication of the physical embodiment of the integrated circuit using transistors, routing resources, etc.
Netlists for integrated circuit designs can represent a particular integrated circuit in different levels of abstraction, such as the register transfer level (RTL) and the logical level, using a hardware description language (HDL), also called high level design language. Design engineers typically define netlists using one of two popular forms of HDL, Verilog, and VHDL. Via the HDL defined netlist, the integrated circuit can be represented by different layers of abstractions (e.g., behavioral levels, structural levels, and gate levels). For example, an RTL level netlist is an intermediary level of abstraction between the behavioral and structural levels. HDL descriptions (e.g., netlists) can represent all of these levels.
The HDL description is used along with a set of circuit constraints as an input to a computer-implemented compiler (also called a “silicon compiler” or “design compiler”). The compiler program processes the HDL description of the integrated circuit and generates therefrom a low-level netlist comprised of detailed lists of logic components and the interconnections between these components. The components specified by the netlist can include primitive cells such as full-adders, NAND gates, NOR gates, XOR gates, latches, and D-flip flops, etc., and their interconnections.
Prior art
FIG. 1
shows an exemplary flow chart diagram of a typical prior art logic synthesis process
100
. Process
100
is implemented in a CAD environment within a computer system. Process
100
begins in step
101
, where an HDL description of the integrated circuit is received (e.g., from a design application). In step
102
, the HDL description is compiled by a specialized HDL compiler tool. The compiler (also called an HDL compiler, RTL synthesizer, or architectural optimizer) inputs the HDL description and compiles this description using logic optimization procedures and mapping procedures which interface with a technology-dependent cell library
103
(e.g., from LSI, VLSI, TI or Xilinx technologies, etc.). The cell library
103
contains specific information regarding the cells of the specific technology selected. Such information includes, for example, the cell logic, number of gates, area consumption, power consumption, pin descriptions, etc., for each cell in the library
103
. The compiling procedure of step
102
ultimately generates a gate level mapped netlist that is technology dependent, having cells specifically selected in accordance with the particular manufacturing technology being used to fabricate the integrated circuit device.
In step
104
, the compiler then performs optimization processing on the resulting mapped netlist from step
102
. The optimization processing is performed using a set of design constraints
105
. The gate level netlist received from step
102
is processed in light of the design constraints
105
. Design constraints
105
include the set of performance constraints applicable to the design, which typically include timing, area, power consumption, and other performance-related limitations that the compiler (e.g., in step
102
) will attempt to satisfy when synthesizing the integrated circuit design. These constraints can also include non-performance related constraints such as structural and routing constraints.
Referring still to step
104
of prior art
FIG. 1
, constraints are used to guide the optimization and mapping of a design towards feasible realization in terms of area, performance, costs, testability, power consumption, and other physical limitations. The constraints provide the goals for the optimization and synthesis tools to achieve. Performance and area constraints are. the two most common constraints. For example, for behavioral synthesis, the area constraints are usually specified at the architectural level where a designer specifies the number of function units, registers, and busses to be used on the RTL structure. The timing constraints are specified as the expected clock frequency of each clock signal.
Technology libraries
103
and design constraints
105
typically contain all the information needed by the synthesis tool to make correct choices in building the structure of the integrated circuit. They contain descriptions of the behavior of a cell and information such as the area of the cell, the timing of the cell, the capacitance loading of the cell, the rise and fall delay values for the basic cells, etc. The objective of the optimization process is to generate the most efficient detailed layout of the integrated circuit possible.
Subsequently, in step
106
, the resulting optimized netlist is simulated to verify its performance. In step
107
, if the optimized netlist performs as desired, the resulting verified netlist proceeds to subsequent fabrication processing and is fabricated into a resulting integrated circuit device. However, should performance of the optimized netlist prove sub-standard, additional optimization processing and simulation is performed until the netlist can be verified.
The increasing size and complexity of modern integrated circuit devices lead to numerous problems with prior art process
100
. The compiling and optimization of large integrated circuit designs are very resource and computer intensive. The compiling and optimization a large integrated circuit designs typically require one, or more, of the most powerful CAD workstations. Large amounts of memory required to store the details regarding the various aspects of the netlist and large amounts of CPU time are required to perform the various compilation and optimization routines on the netlist.
Thus, large complex integrated circuit designs do not lend themselves to efficient optimization using prior art processes, such as process
100
. Optimization processing on large design as shown by t
Lee Jr. Granvill D
Siek Vuthe
Synopsys Inc.
Wagner , Murabito & Hao LLP
LandOfFree
Method and system for circuit design top level and block... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for circuit design top level and block..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for circuit design top level and block... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2987292