Process for preparing Cu damascene interconnection

Details Process for preparing Cu damascene interconnection Process for preparing Cu damascene interconnection

2002-03-28

2002-11-26

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S623000, C438S637000, C438S640000, C438S673000, C438S687000, C438S692000

Reexamination Certificate

active

06486057

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a process for preparing a Cu damascene interconnection, particularly a process for preparing a Cu damascene interconnection with an improved yield.
BACKGROUND OF THE INVENTION
In the damascene of copper in a low dielectric material, a copper line structure is formed by forming trenches in a low dielectric layer by using an active ionic etching, depositing copper on the whole surface (including filling the trench with copper), and using a chemical mechanical polishing (CMP) to polish off the copper on the surface and leaving copper in the trenches.
A photoresist is used as a mask layer when the active ionic etching is carried out. In order to protect the organic low dielectric layer from damage during the stripping of the photoresist mask layer, a passivation layer is required between the photoresist and the organic low dielectric layer [J. M. Neirynck, R. J. Gutmann, and S. P. Murarka, J. Electrochem. Soc., 1602, (1999); D. T. Price, R. J. Gutmann, and S. P. Murarka, Thin Solid Films, 308-309, 523 (1997)]. However, due to a poor adhesion between the passivation layer and the low dielectric layer, the deposited copper layer is torn off from the surface and the trenches during the CMP process. As a result, a copper damascene interconnection can not be completed.
SUMMARY OF THE INVENTION
The present invention provides a process for preparing a Cu damascene interconnection, which comprises forming a low-K dielectric layer on a substrate; forming a passivation layer on said low-K dielectric layer; forming a plurality of trenches on said low-K dielectric layer/passivation layer; forming a pad oxidation layer on the inner walls of each of said plurality of trenches; forming a barrier metal layer on said pad oxidation layer; depositing copper on the resulting structure; and chemical mechanical polishing said copper until said passivation layer is exposed, thereby forming a Cu damascene interconnection on said low-K dielectric layer, characterized in subjecting said passivation layer/low-K dielectric layer with a N
2
O plasma annealing prior to the formation of said plurality of trenches.
The present invention uses said N
2
O plasma annealing to improve the yield of the process for preparing a Cu damascene interconnection.
Preferably, said N
2
O plasma annealing uses the following conditions: N
2
O flow rate 50~1000 sccm, pressure 10~1000 mTorr, temperature of plate 20~450° C., radio frequency power 50~1000 W, and processing time 1~100 minutes.
Preferably, said low-K dielectric layer is hydrogen silsesquiuxane or methyl silsesquioxane.
Preferably, said passivation layer is SiO
2
or SiNx, wherein 0<x<1.4. More preferably, said passivation layer is SiO
2
, particularly a SiO
2
deposited by a chemical vapor phase deposition (CVD).


REFERENCES:
patent: 6184126 (2001-02-01), Lee et al.
patent: 6224758 (2001-05-01), Jainek et al.
patent: 6251753 (2001-06-01), Yeh et al.
patent: 6277755 (2001-08-01), Chen et al.
patent: 6413879 (2002-07-01), Maeda

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