Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2000-12-28
2002-10-22
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S200000, C711S154000, C712S207000
Reexamination Certificate
active
06470435
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to computer architecture. In particular, the invention relates to register renaming.
2. Description of Related Art
A processor employing out of order execution may experience data hazards with respect to register operands. A method for handling these hazards is register renaming. In register renaming, the processor implements a set of physical registers. Typically, the number of physical registers is greater than the number of logical registers referenced by instructions. As instructions are issued, physical registers are assigned to the destination register operands of the instructions. A physical register number identifying the assigned physical register is provided for each destination operand. The correspondence between the physical registers and logical registers is kept track of.
Register renaming presents difficulties when instructions experience branch misprediction or exception conditions. This refers to an error in the execution of instructions which requires subsequent instructions to be discarded and instruction fetch to be started at a different address. Processors may perform branch prediction to speculatively fetch, issue, and execute instructions subsequent to conditional branch instructions. If the prediction is incorrect or the exception is not handle properly, the instructions subsequent to the branch instruction are discarded and instructions are fetched according to execution of the branch instruction. Additional exception conditions may include address translation errors for addresses of memory operands and other architectural or micro-architectural error conditions.
Because register renaming may have been applied to instructions which are subsequently discarded due to an exception, the mapping of logical registers to physical registers should be recovered to a state consistent with the instruction experiencing the exception.
Existing techniques for rename recovery include recovery at retirement, use of a re-order buffer, and use of a branch rename table. The recovery at retirement approach transfers all state from a retire table to a speculative rename table. The disadvantages of this approach include penalty for additional time to prepare the retire table because rename recovery cannot be started until the mispredicted branch is retired.
The re-order buffer approach keeps track of rename information at each unresolved branch. This approach may require a large implementation area, resulting in inefficient use of area. The branch rename table approach stores the rename state at the oldest unresolved branch. This approach is generally not able to accommodate other exception recovery cases and may not offer the best performance speed.
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Doweck Jacob
Kuttanna Belliappa
Samra Nicholas G.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Thai Tuan V.
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