Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-08-15
2002-12-03
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06490717
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to incremental compilation of changed electronic designs. More specifically, it relates to methods, machine readable media, and apparatuses for delineating the range of influence of a design change in an unsynthesized netlist.
Electronic design automation (“EDA”) is becoming increasingly complicated and time consuming, due in part to the greatly increasing size and complexity of the electronic devices designed by EDA tools. Such devices include general purpose microprocessors as well as custom logic devices including Application Specific Integrated Circuits (“ASICs”). Examples of ASICs include non-programmable gate arrays, field programmable gate arrays (“FPGAs”), and complex programmable logic devices (“PLDs” or “CPLDs”). The design of even the simplest of these devices typically involves generation of a high level design, logic simulation, generation of a network, timing simulation, etc. Usually, timing simulation cannot be performed until the design has been compiled to the point where the various gate level entities are synthesized and placed and the lines therebetween routed on a target hardware device. This compilation requires that a design project (or a significant piece of it) be functionally completed.
Meeting timing requirements is essential to the correct operation of an integrated circuit. For example, for a plurality of D-type flip-flops (“DFFs”) to feed through some logic to another plurality of DFFs, it is generally required that the signals form the first set of DFFs must finish propagating through any intermediate logic and have settled to their final state on the D-input of each of the destination DFFs before the next rising edge of the clock. (In fact they must finish before the next clock edge by an amount known as the setup delay of the register Tsu.) If the delay through the resulting logic is greater than the time between rising clock edges, then the state that the desitination DFFs will hold on the next clock edge will be undefined.
Quite typically, a designer (or the compiler itself) will modify a design after an initial compilation. This may be required when a timing simulation conducted after compilation indicates a problem. Or, the product requirements may change in the middle of the device's development. Regardless of why a design change is necessary, that change requires a recompile. Unfortunately, each compilation consumes significant time, so multiple recompiles translates to significantly longer development times. This can greatly slow the time to market for an integrated circuit under design. Because PLDs rely on a short time to market as a major selling point, slow development can erase any commercial advantage.
The problem is compounded because maximum CPLD device sizes are increasing at a speed slightly greater than that predicted by Moore's law (i.e., each new chip contains roughly twice as much capacity as its predecessor, and each chip is released within 18-24 months of the previous chip). If compilation time was a linear function of design size then it would be expected that the time to compile the largest device on the most powerful computer would remain approximately constant. Unfortunately, compile times are typically proportional to n
2
, where n is the number of logic elements on a device. This means that a design twice as big takes four times as long to compile. Consequently, the compile times for the largest devices are accelerating. It is not uncommon for large projects to compile for about 24 hours or more on a modern workstation. Obviously, the fastest compilers will become critical components of integrated circuit design environments.
Large designs often benefit from performing and comparing multiple compilations, each based upon a different compilation parameters or slight design changes. Obviously, given long compile times, most designers do not have the luxury of running multiple compilations for comparison.
An important advance in the effort to reduce compilation time for large devices is incremental compilation. In essence, incremental compilation involves using a previously compiled design such that only a fraction of that design must be recompiled after a user or compiler makes one or more changes to the design. Incremental compilation requires at least two steps: (1) delineating a sphere of influence of user changes in a previously compiled design (the sphere of influence typically being defined within a netlist), and (2) recompiling the logic from within this sphere of influence into appropriate logic elements available within a target hardware device. To maximize efficiency, the compiler should limit recompile to a minimum region of the electronic design (and a corresponding region of a target hardware device) which is directly affected by the design change.
One suitable technique for recompiling the changed logic (step 2) involves resynthesizing the changed logic, remapping the changed logic to logic elements (defined by the target hardware), and then fitting the remapped logic cells at positions on the target hardware device. Preferably, during incremental refitting, unchanged logic cells remain fixed in the same hardware positions that they occupied after the original compilation. If the compiler cannot fit the new design under this constraint, the compiler gradually relaxes the constraints on movement of unchanged logic cells. This technique is described in U.S. patent application Ser. No. 08/958,436 filed on the same day as the instant patent application, naming J. Tse et al. as inventors and entitled “FITTING FOR INCREMENTAL COMPILATION OF ELECTRONIC DESIGNS.” That application was previously incorporated herein by reference for all purposes.
At this point, an effective incremental compiler cannot be realized until development of an efficient technique for delineating the portion of an electronic design influenced by a user's design change. Thus, there is a need for an incremental recompile technique that efficiently and correctly identifies logic cells that are effected by a user's design changes.
SUMMARY OF THE INVENTION
The present invention provides a technique and associated compiler for delineating those logic gates in an electronic design that should be resynthesized during an incremental recompile. It accomplishes this by identifying those logic gates within a netlist that are new or are affected by the modification. To understand how this works, recognize that an “original electronic design” has already been fully compiled. Now, a user has made one or more changes to the original electronic design to produce a “changed electronic design.” This invention identifies—at the netlist level—where those changes lie and how widely effects of those changes propagate. The gates flagged as changed are then recompiled, while the remainder of the gates from the original design are left as is. The invention operates such that a minimal number of changed gates are identified while capturing all gates necessary to accurately program the user's changed electronic design. The segment of a netlist encompassing this minimal number of changed gates is referred to herein as a “sub-netlist.”
In one aspect, the invention may be characterized as a method—typically implemented on a compiler—having the following sequence of operations: (a) receiving an unsynthesized netlist for an original electronic design, a synthesized netlist for the original electronic design, and an unsynthesized netlist for a changed electronic design; (b) identifying one or more new logic nodes in the unsynthesized netlist for the changed electronic design that have been directly changed from the unsynthesized netlist for the original electronic design; (c) in the unsynthesized netlist for the changed electronic design, tracing signal propagation paths between at least one of the new logic nodes and one or more external nodes, such that nodes encountered on the signal propagation path are designated as affected nodes which together with the one or more new logic nodes form the
Heile Francis B.
Khalaf Marwan Adel
Mendel David Wolk
Pedersen Bruce
Altera Corporation
Beyer Weaver & Thomas LLP
Garbowski Leigh Marie
Siek Vuthe
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