Method of making a semiconductor device

Details Method of making a semiconductor device Method of making a semiconductor device

2000-09-19

2002-12-03

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S629000, C438S700000

Reexamination Certificate

active

06489234

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods of making a semiconductor device (hereinafter “LSI device”).
2. Description of the Related Art
An LSI device has many technical requirements such as high-speeds, low power consumption, versatile functions, and high integration degrees, and it is necessary to develop a circuit pattern which has no less functions and/or better electrical characteristics at a smaller occupied area than those of the current LSI devices.
In the process for making LSI devices, a number of treatments or photolithographic techniques (hereinafter “lithographic techniques”) are applied to the surface of a semiconductor silicon wafer (hereinafter “wafer”) to form a microscopic circuit pattern thereon.
A photoresist pattern corresponding to the circuit pattern formed by lithographic technique is used as a masking material to perform etching a thin film material or injecting an impurity ion. By repeating such treatments for a number of times, a desired LSI circuit pattern is formed.
However, the resolution with which the microscopic circuit pattern is formed in the lithographic technique and the circuit pattern is positioned on the layer is approaching the limit. Consequently, the formed photoresist pattern fails to meet the required working precision for the LSI circuit pattern.
In FIGS.
2
(
a
) and
3
(
a
), a silicon monocrystal substrate (hereinafter “silicon substrate”) is indicated by reference numeral
21
. A field oxide (SiO
2
) film
22
having a thickness of 2000-8000 Å is formed by the well known LOCOS process. A channel stopper or impurity diffusion region (not shown) is provided in the silicon substrate
21
to form an electrical insulation region.
An electrode pattern
23
is made from a polycrystal silicon (hereinafter “polysilicon”) having a thickness of 1000-4000 Å or a film containing a metal of high melting point, such as tungsten, molybdenum, or titanium, or a eutectic film of silicon and a metal having a high melting point. A thin silicon oxide film (not shown) having a thickness of 50-500 Å is made under the electrode pattern
23
.
An interlayer insulation or oxide film
24
having a thickness of 1000-8000 Å is formed. A photoresist film
25
is formed by the lithographic technique to provide a photoresist pattern
26
. The photoresist film
25
is used as a mask to etch a contact pattern or hole
26
′ in the interlayer insulation film
24
.
Problems arising from the fact that the lithographic technique reaches its precision limit will be described with reference to FIGS.
2
(
b
)-(
d
) and
3
(
b
)-(
d
).
In FIGS.
2
(
b
) and
3
(
b
), the photoresist pattern
26
a
formed by the lithographic technique is slightly offset from the underground pattern to make contact with the electrode pattern
23
.
Consequently, a portion of the contact pattern
26
a
′ is formed on the edge of the electrode pattern
23
. As a result, a wiring material formed within the contact pattern
26
a
′ makes contact with the electrode pattern
23
as shown by A in FIG.
3
(
b
), providing a electrical circuit failure or defect LSI device.
This problem results from the fact that the photoresist pattern
26
a
is formed at a slightly offset position by the lithographic technique. This problem has been negligible in making LSI devices having a circuit pattern dimension of 0.5 &mgr;m or more. However, this problem is no longer negligible for a circuit pattern dimension of 0.4 &mgr;m or less.
In FIGS.
2
(
c
) and
3
(
c
), the contact pattern
26
is slightly offset in the direction opposite to that of FIGS.
2
(
b
) and
3
(
b
). The contact pattern
26
b
formed on the photoresist film
25
is offset from the electrode pattern
23
and laid on the edge of the field oxide film
22
. Consequently, the contact pattern
26
b
′ formed in the interlayer insulation film
24
cuts a portion of the field oxide film
22
as shown by B in FIG.
3
(
c
). As a result, a portion of the channel stopper (not shown) formed under the field oxide film
22
is exposed.
When a wiring material is formed, the exposed portion is prone to an electrical leak to the silicon substrate
21
, providing a defective LSI device.
In FIGS.
2
(
d
) and
3
(
d
), the contact pattern
26
c
formed on the photoresist film
25
is larger than the designed pattern.
Similarly to the problems in FIGS.
2
(
b
),
2
(
c
),
3
(
b
), and
3
(
c
), the wiring material formed within the contact pattern
26
c
′ makes connection with the electrode pattern
23
as shown by C in FIG.
3
(
d
) or allows an electrical leak from the field oxide film
22
to the silicon substrate
21
as shown by C′ in FIG.
3
(
d
).
In addition, the precision problem, such as the too large contact pattern
26
c
′, reduces the tolerance for positioning offset so that the yield of LSI devices is reduced by both of the factors of positioning and dimension precision. A number of measures for minimizing these disadvantages have been proposed.
A representative example will be described with reference to FIGS.
4
(
a
)-(
d
).
In FIG.
4
(
a
), reference numeral
21
denotes a semiconductor substrate,
24
an interlayer insulation film,
25
a photoresist film,
26
a photoresist pattern formed in the photoresist film
25
, and
26
′ a contact pattern formed in the interlayer insulation film
24
.
A substrate portion
21
′ is exposed by etching the interlayer insulation film
24
, and its surface is slightly damaged by the etching process. This damage is omitted in FIGS.
2
(
a
)-(
d
) and
3
(
a
)-(
d
).
In FIG.
4
(
b
), the photoresist film
25
is removed.
In FIG.
4
(
c
), an insulation film material or silicon oxide film
41
is formed on the interlayer insulation film
24
and within the contact pattern
26
′ by the chemical vapor deposition (CVD) process to a thickness of 600-4000 Å.
In FIG.
4
(
d
), an anisotropic etching process is applied to the entire surface of the oxide film
41
to proceed in the perpendicular direction (hereinafter “etchback process”). Consequently, only the oxide films
41
′ on the side walls of the contact pattern
26
′ remain.
Consequently, the diameter of the contact pattern or hole
26
′ is reduced by the side wall oxide films
41
′ to thereby minimize the above problems in
FIGS. 2 and 3
. In this method, however, the silicon substrate portion
21
″ is exposed again upon formation of the side wall oxide film
41
′ so that the etching damage is accumulated.
In addition, the thickness of the side wall oxide film
41
′ is determined by the thickness of the oxide film
41
formed by the CVD process, which in return determines the effective size of the final contact pattern
26
′. Consequently, in order to minimize the problems of
FIGS. 2 and 3
by reducing the size of the contact pattern
26
′, it is desired to form a thick oxide film
41
by the CVD process.
However, the contact pattern
26
′ itself is very small and can be formed too small to provide satisfactory etchback process as shown at
27
in FIG.
5
(
a
) owing to the precision problem of the lithographic technique. Consequently, a defective opening
41
″ of the contact pattern
27
can be made as shown in FIG.
5
(
b
).
The defective opening
27
can also result from variations in the thickness of the oxide film
41
formed by the CVD process, leading to a defective LSI device.
If the etchback process is increased to reduce the frequency that the defective opening of the contact pattern
27
is produced, the damage to the substrate portion
21
″ exposed by the etching process in FIG.
4
(
d
) increases.
The damage, which appeared to be caused by impurities injected in the etching process or crystal defect produced in the silicon substrate
21
, increases variations in the electrical resistance at the contact or increases the electrical resistance. Such variations in the electrical resistance are no longer negligible for submicron technolo

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