Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
2000-02-25
2002-11-19
Letscher, Geraldine (Department: 1752)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S022000, C430S030000, C430S313000
Reexamination Certificate
active
06482572
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor devices and, more specifically, to alignment during semiconductor fabrication. More particularly still, the present invention relates to the use of a resist latent image as a diffraction grating for the aligning and patterning of field oxide, and relates to the use of field oxide step heights for alignment during the fabrication of circuit devices.
2. State of the Art
One area involving constant improvement in semiconductor device fabrication is in the area of photolithography. Presently utilized semiconductor device processing methods require numerous photolithography steps. Thus, photolithography is one of the most critical operations in semiconductor device processing.
Photolithography is essentially a patterning process which determines the horizontal dimensions on the various components of the semiconductor devices (i.e., circuit components) by creating a mask on a particular material layer (disposed on or over a semiconductor wafer) of the semiconductor device and etching portions of the material layer through the mask to form a pattern on that material layer. The dimensions of the pattern are referred to as the image sizes of the circuit components.
Since the material layers are sequentially built up and patterned to form the semiconductor device, the photolithographic patterning process requires proper placement or alignment of each pattern on each particular material layer of the semiconductor device. The patterns formed on the various material layers must be correctly aligned and the individual parts of the circuit components must be correctly positioned relative to each other for the semiconductor device to function properly.
Naturally, the image size and pattern alignment in photolithography are interrelated. As the image size decreases, the alignment of the patterns must be more precise. Of course, image size will continue to decrease, because increased miniaturization of components and greater packaging density of integrated circuits are ongoing goals of the computer industry. Thus, as circuitry components become smaller and smaller, alignment must become more precise during masking steps to minimize the misalignment between patterned, material layers utilized in forming the circuitry components.
Most alignment schemes require the use of alignment targets that are defined on the semiconductor wafers and/or a previous material layer. One such scheme involves two alignment targets that are defined on the semiconductor wafer with all subsequent layers being aligned, either directly or indirectly, with these alignment targets. These alignment targets are used to diffract a laser alignment beam generated by a photolithographic machine, commonly known as a wafer stepper, during the masking process. The diffraction pattern is received by the wafer stepper and the relative positions of the semiconductor wafer and a photolithographic mask are adjusted accordingly so that the patterns from the photolithographic mask are transferred to the semiconductor wafer in the precise location as desired.
Subsequent layers, such as conductive material (i.e., metallization) or dielectric layers, are formed during the circuit fabrication in a similar fashion. In order to minimize misalignment between layers, it is important that the topography of these alignment targets be replicated from one layer to the next, since the locations of the resulting patterns on each material layer are formed based on the precise registration between the photolithographic mask and the alignment targets on the previous material layer.
For metallization layers, it is generally important to provide a surface that is as flat or planar as possible. Thus, the surface of the layer is smooth in preparation for subsequent metallization layers by the process known as planarization. Conventional planarization techniques include plasma etching or the reactive ion etching (RIE) of oxides with a resist planarizing medium. New techniques include abrasive planarizing in the form of chemical-mechanical polishing/planarizing (“CMP”) which involves holding the semiconductor wafer against a rotating polishing pad wetted with a silica-based alkaline slurry and at the same time applying pressure. The CMP techniques provide a global planarization that covers the whole surface of the semiconductor wafer. Since the planarization range is large, the alignment targets on a newly formed layer on the semiconductor wafer will lose their steps after it is planarized. The CMP technique fails to replicate the alignment targets on the previous layer that is beneath the newly formed layer. This is acceptable only if the planarized, newly formed layer is transparent, such as in the case of silicon dioxide, since the laser or alignment beam from a wafer stepper and the corresponding diffraction pattern can pass through such a transparent layer. However, when the planarized, newly formed layer is highly reflective or opaque, such as in the case of a metal layer, the alignment targets are not visible to the wafer stepper. In such a case, new alignment targets have to be formed on the newly formed layers using a process commonly known as the window mask process.
Window mask processing involves exposing the alignment targets only while the remaining semiconductor wafer surface is covered by photoresist. The semiconductor wafer is then subjected to an oxide step of sufficient duration so that the amount of silicon dioxide removed during this etch, plus the amount of silicon dioxide to be removed during the subsequent etch, exposes the step pattern of the underlying target. This allows the metal to replicate the topography of the step patterns of the underlying alignment targets when the metal is deposited. This technique forms a new set of alignment targets. Accordingly, the wafer stepper is able to perform alignment between a photolithographic mask, the semiconductor wafer and the next photolithic process.
By way of example only, the following discussion will focus on the formation of a twin-well CMOS (Complementary Metal Oxide Semiconductor) structure using standard alignment marks.
FIG. 21
illustrates a semiconductor wafer
202
in which alignment marks
204
have been formed in an active surface
206
at a location proximate an edge
208
of the semiconductor wafer
202
. These alignment marks
204
are used to align the patterning of masks and implantation tools, as known in the art, to form p-wells
212
and n-wells
214
abutting the active surface
206
of the semiconductor wafer
202
. The individual electrical devices are generally isolated using a LOCOS (LOCal Oxidation of Silicon) technique.
The LOCOS technique begins with forming a layer of silicon dioxide
218
, usually between about 20 and 50 nm thick, on the active surface
206
of the semiconductor substrate
202
, as shown in FIG.
22
. After the formation of the silicon dioxide layer
218
, a layer of silicon nitride
222
, usually between about 100 and 200 nm thick, is deposited, generally by CVD, over the silicon dioxide layer
218
to function as an oxidation mask. The alignment marks
204
must be re-exposed in order that they are detected for alignment purposes. This can be achieved by removing a portion of the silicon nitride layer
222
and silicon dioxide layer
218
over the alignment marks
204
.
Active areas
232
are then defined with photolithographic and etch steps illustrated in
FIGS. 23 through 27
. As shown in
FIG. 23
, a photoresist layer
224
is patterned on the silicon nitride layer
222
to protect all of the areas where active areas will be formed, wherein the photoresist layer
224
pattern is aligned using the alignment marks
204
. The silicon nitride layer
222
and the silicon dioxide layer
218
are then etched, and any remaining photoresist layer
224
is removed, as shown in
FIG. 24. A
barrier layer
225
is preferably formed over the alignment marks
204
to prevent silicon dioxide formation on the alignment mark
Honeycutt Jeffrey W.
McDonald Steven M.
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