Low switching activity dynamic driver for high performance...

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor

Reexamination Certificate

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Details

C326S093000, C326S095000, C327S208000, C327S407000, C327S408000

Reexamination Certificate

active

06351150

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to interconnects for use in digital processing devices and, more particularly, to interconnects that utilize dynamic driver techniques.
BACKGROUND OF THE INVENTION
The integration density of circuit elements within integrated circuits is continuously increasing. The resulting reduction in size of circuit elements and the accompanying on-die heat dissipation problems has created interest in developing low power, low voltage circuit technologies that maintain or improve past circuit performance. One performance bottleneck that has arisen with increased integration density relates to the point to point interconnects within an integrated circuit. One of the primary reasons for this bottleneck is because the capacitance per unit length of such interconnects, which is dominated by sidewall fringing and coupling, increases hyperbolically with lateral dimension scaling.
To overcome problems related to increased interconnect capacitance due to scaling, a change to dynamic interconnect driver technologies has been proposed. In a dynamic driver circuit, the driver output node is only able to transition in one direction (i.e., monotonically) during normal driver operation, thus reducing the interconnect's worst-case coupling capacitance by half. This is normally implemented by precharging the driver output node to the supply voltage before considering a present driver input data bit and then either discharging or maintaining the charge on the output node based on the value of the driver input bit. Thus, the output potential of the driver either remains the same or moves in a single direction after the current input bit is considered. In an alternative approach, the driver output node can be discharged initially and then be charged or remain discharged based on the value of the current input bit.
The reduction in capacitance achieved by utilizing dynamic driver techniques can provide a significant improvement in, for example, driver performance, interconnect RC delay, peak current, and/or switched capacitance per transition. However, the need to repeatedly precharge and evaluate the dynamic driver can cause substantial dynamic power loss during periods of low data switching activity on the interconnect. Periods of low data switching activity are common on data busses and other transmission media within digital data processing devices. Thus, the use of dynamic driver techniques within such busses can significantly increase power consumption (and the heat dissipation problems associated therewith) within these processing devices.
Therefore, there is a need for a method and apparatus that allows the benefits of dynamic driver circuits to be realized within an interconnect without the high power loss associated with low data switching activity.


REFERENCES:
patent: 6005417 (1999-12-01), Mehta et al.
patent: 6028814 (2000-02-01), Lim
patent: 6140843 (2000-10-01), Howard

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