Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-12-23
2002-10-22
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06470477
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor feature layout generation, and more particularly, to intelligent computer implemented methods for inspecting and modifying features of a given layout design to comply with defined constraints.
2. Description of the Related Art
Today's semiconductor devices are continually being pushed to meet stricter demands. As devices using this technology inundate the marketplace, consumers are continuing to place higher demands on these devices. These demands include smaller, more compact devices with greater functionality.
In order to meet these demands, semiconductor devices are becoming smaller and smaller. These smaller devices use tighter design tolerances with more demanding design rules in order to allow for their size. The smaller devices allow for more compact integration of circuitry on a semiconductor chip. Also, the smaller designs require less space for greater functionality within a circuit. The design tolerances used within semiconductor devices are commonly associated to a particular micron technology. Thus, each type of micron technology requires conformance with a particular set of design rules The design rules for one micron technology (e.g., 0.18 micron technology) are necessarily different than other micron technologies (e.g., 0.25 micron technology).
The design tolerances and accompanying design rules are implemented at the design level using computer aided design (CAD) tools. As is well known, design engineers typically use cell libraries to construct a desired integrated circuit device. The cell libraries are typically optimized for one micron technology or another. In some cases, it may be desired to implement cells from different libraries, such that some cells include features designed in accordance with one set of design rules and other cells use another set of design rules. When a given design initially has cells with different design rules, fabrication problems can arise. For process compatibility, it is well known that all cells of a given design have the same design rules. To comply with this requirement, design engineers use software tools to inspect and change the physical sizes of features in certain cells to ensure that all cells are of the same micron technology. For instance, one of the many cells is a 0.25 micron technology cell and all others are 0.18 micron technology cells, the features of the 0.25 micron technology cells will be modified (e.g., resized) to convert them into 0.18 micron technology features. This conversion is generally performed directly on flat data. Flat data is referred to herein as data representing the geometric features on the different levels of an integrated circuit device. For example, some devices may include several dozen mask layouts, each representing a plurality of geometric features (e.g., interconnect lines, contact features, via features, gate electrode features, etc.) An exemplary mask generation tool used to perform such modifications may be a software product named CATS (computer aided transcription system), which is available from Transcription Enterprises, L.T.D., of Los Gatos, Calif.
It should be noted that such software is programmed to inspect and modify each feature in the design one at a time. This is true even when the same geometric feature is repetitively used throughout a given design. For example, if a via hole feature is resized on one part of a design, that same resizing operation must be repeated for all other via holes. Although this process does not appear to be complex, integrated circuit designs have many thousands of features that repeat throughout a design. Consequently, having to inspect each feature and operate a particular resizing operation repetitively can be quite time consuming. In some cases, the process of modifying features can take up to a couple of days of computer processing time.
In accordance with the prior art, once the features have been modified, it is not possible to use standard design rule checkers (DRCs) to review whether or not the newly modified features comply with their new design rules. For example, if one or more 0.25 micron cells (each cell including a plurality of features on different levels) were modified down to a 0.18 micron technology, then a DRC checker would not be able to check whether the newly created 0.18 micron technology features meet the 0.18 micron technology design rules. This is because DRC checkers are only able to examine designs originally created in accordance with one micron technology or another. Also, when programs such as CATS are used to modify a design, the modified features may have new imperfections that cannot be examined by DRC checkers.
Because designs have thousands or millions of features, engineers typically find it impossible to manually inspect the entire design. Thus, many times engineers proceed with the fabrication of the reticles incorporating the features designs and only hope that the designs function as intended. Of course, if the design fails, a substantial waste of manufacturing time and materials will already have been expended.
In view of the foregoing, there is a need for a computer implemented method which can intelligently modify design features of different cells to conform to one set design rules.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing a computer implemented method which can intelligently modify design features selected by a user to conform to one set of design rules selected by a user. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, as apparatus, a system, a device, a method or a computer readable media. Several inventive embodiments of the present invention are described below.
In one embodiment, a method for converting physical features of an integrated circuit design to a uniform micron technology is disclosed. The integrated circuit design is defined by a plurality of cells with each cell being defined by one or more micron technologies. A user is prompted to provide key design rules which define desired features associated with one or more micron technologies. The method comprises examining a layout database which has a hierarchical structure for the integrated circuit design. After examining the layout database, a top cell from the layout data base of the integrated circuit design is identified. Then, the method descends through a first branch of the hierarchical structure of the layout database to a lowest cell in the first branch. Once the lowest cell is reached, a determination is made as to whether physical data of the user desired features have been previously processed for the lowest cell. Next, it is determined if the physical data of the user desired features for the lowest cell comply with the user specified uniform micron technology. The physical data of the user desired features is then processed if the lowest cell has not been previously processed and does not comply with the uniform micron technology. Once one subcell is processed, all other instances of that subcell are also instantly considered processed. Therefore, the method will skip those subcells and only process non-processed subcells. The converted and checked layout data of the IC design can then be converted into reticles for IC fabrication.
In another embodiment, a method for the efficient conversion of features in an integrated circuit design is disclosed. A user selects the features to be converted in the integrated circuit design. The user also selects the uniform micron technology to be used for the features. The method comprises providing an integrated circuit design that is defined by a hierarchical layout database of multiple cells. Then, a top cell of the hierarchical layout database and subcells nested from the top cell are identified. After the subcells are identified, the method proceeds to descend to a lowest subcell of the subcells. Once the lowest subcell is reached, a determination is mad
Do Thuan
Koninklijke Philips Electronics , N.V.
Smith Matthew
Zawilski Peter
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