Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-29
2002-12-10
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S315000
Reexamination Certificate
active
06492676
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a gate electrode of an insulated gate transistor and an electrode of a capacitor.
2. Description of the Background Art
In an insulated gate transistor according to the prior art, so-called scaling has been performed in which an operating supply voltage is set low from the viewpoint of hot-carrier resistance and reliability of a gate insulation film along with a finer structure of an element.
In a short channel transistor having a small channel length, a saturation current IDsat is generally proportional to a difference (VG−Vth) between a gate voltage VG and a threshold voltage Vth. For this reason, if the gate voltage VG is equal to a supply voltage VDD, the saturation current IDsat is proportional to a difference (VDD−Vth) between the supply voltage and the threshold voltage.
In order to suppress a short circuit current of a circuit and surely turn off a transistor, a current flowing between a gate and a source when the gate voltage VG is equal to or smaller than the threshold voltage, that is, a subthreshold current should be suppressed.
A current flowing when the gate voltage is 0V, that is, an OFF-state current IOFF is calculated by Equation 1, wherein a gate voltage VG necessary for increasing the subthreshold current by one digit, that is, a subthreshold coefficient is represented by S and a threshold voltage Vth is set to VG applied when a drain current ID for 1.0 &mgr;m of a gate width W is equal to 0.1 &mgr;A:
The subthreshold coefficient S is physically calculated by Equation 2:
IOFF=
0.1 &mgr;A×10
−(Vth/S)
(1)
S
=
kT
q
×
log
e
10
×
(
1
+
CB
+
Cit
COX
)
(
2
)
wherein k represents a Boltzmann's constant, q represents an elementary charge, e represents a base of a natural logarithm, T represents an absolute temperature, CB represents a depletion layer capacitance between a channel and a substrate, Cit represents a capacitance based on an interface state of a gate oxide film, and COX represents a capacitance of the gate oxide film.
If CB and Cit are equal to 0, S=60 mV/decade is obtained at a room temperature of 300 K. If CB and Cit are not equal to 0, S=70 to 100 mV/decade is obtained. For example, when an OFF-state current IOFF for a gate width of 1.0 &mgr;m in a general transistor is set to 0.1 pA and a subthreshold coefficient S is set to 85 mV/decade, Vth is set to 0.51V by Equation 3 when a drain voltage VD is a supply voltage VDD. This value is not varied when a standard of the OFF-state current IOFF and a value of the subthreshold coefficient S are not changed even if the supply voltage VDD is reduced.
Vth
=
S
×
log
e
0.1
μ
A
0.1
p
A
(
3
)
Accordingly, even if the supply voltage VDD is set low when making a finer structure, the threshold voltage Vth is not subjected to the scaling because the OFF-state current IOFF is restricted. On the other hand, the saturation current IDsat is proportional to (VDD−Vth). Therefore, current driving force is reduced and an operating speed of an element is decreased in some cases when making a finer structure.
In a transistor having a low threshold voltage Vth, an impurity concentration of a channel is low after making a finer structure. For this reason, punch-through is caused so that a current which cannot be controlled by the gate voltage VG flows. Consequently, a circuit performs wrong operation.
In the case where a transistor is used for an output stage of the circuit or the like, a supply voltage VDD
1
applied to the transistor is sometimes set higher than a supply voltage VDD of other circuit portions. In the same transistor, for example, a voltage of 0 V to VDD is applied as a gate voltage VG and a voltage of 0 V to VDD
1
is applied as a drain voltage VD. In this case, a maximum voltage applied to a gate insulation film is VDD
1
if the gate voltage VG is 0 V and the drain voltage VD is VDD
1
. In such a transistor, therefore, a thickness of the gate insulation film should be resistant to an electric field having an intensity obtained by VDD
1
/tOX.
The foregoing will further be described with reference to
FIGS. 72
to
74
. In
FIG. 72
, a P-channel MOS transistor M
1
and an N-channel MOS transistor M
2
form an inverter. An input voltage VIN applied to an input terminal of the inverter has a value of 0 V or 2.5 V. A voltage of 5 V is applied to a source of the transistor M
1
, and a ground voltage VSS (0 V) is applied to a source of the transistor M
2
. With such a structure, an output voltage VOUT is 5 V when the input voltage VIN is 0 V, and a maximum voltage (5 V) is applied between a drain and a gate of the transistor M
2
. At this time, the maximum voltage (5 V) is also applied between a drain and a gate of the transistor M
1
.
In
FIG. 73
, P-channel MOS transistors M
3
and M
5
and N-channel MOS transistors M
4
and M
6
form an OR circuit. The transistors M
4
and M
6
are connected in parallel. Parallel connected elements comprising the transistors M
4
and M
6
, and the transistors M
3
and M
5
are connected in series. A supply voltage VDD is given to a source of the transistor M
5
. A connecting point of drains of the parallel connected elements and the transistor M
3
acts as an output terminal. An input voltage VIN
1
given to gates of the transistors M
3
and M
4
and an input voltage VIN
2
given to gates of the transistors M
5
and M
6
are changed together within a range of 0 V to 2.5 V. For this reason, a maximum voltage (5 V) is applied between gates and drains of the transistors M
4
and M
6
if the input voltages VIN
1
and VIN
2
are 0 V, and the maximum voltage (5 V) is applied between the gate and source of the transistor M
5
if the input voltage VIN
2
is 0 V, for example.
In
FIG. 74
, P-channel MOS transistors M
7
and M
9
and N-channel MOS transistors M
8
and M
10
form a NAND circuit. The transistors M
7
and M
9
are connected in parallel. Parallel connected elements comprising the transistors M
7
and M
9
, and the transistors M
8
and M
10
are connected in series. A supply voltage VDD is given to sources of the transistors M
7
and M
9
. Drains of the transistors M
7
and M
9
are connected to an output terminal. A drain of the transistor M
8
is also connected to the same output terminal. A ground voltage VSS (0 V) is given to a source of the transistor M
10
. An input voltage VIN
1
given to gates of the transistors M
7
and M
8
and an input voltage VIN
2
given to gates of the transistors M
9
and M
10
are changed together within a range of 0 V to 2.5 V. For this reason, a maximum voltage (5 V) is applied between the gate and drain of the transistor M
8
and the maximum voltage is also applied between the gates and drains of the transistors M
7
and M
9
if either of the input voltages VIN
1
and VIN
2
is 0 V, for example.
FIG. 75
typically shows a section of a main part of the insulated gate transistor according to the prior art. In the case where the transistor shown in
FIG. 75
is an N-channel MOS transistor, the reference numeral
1
denotes a P type silicon substrate having a resistivity of several &OHgr;·cms to several tens &OHgr;·cms and a crystallographic axis <100>, the reference numeral
2
denotes a P well formed in the vicinity of a surface of the silicon substrate
1
, the reference numeral
3
denotes a channel dope region which is formed in the P well
2
and serves to control a threshold and to prevent punch-through, the reference numeral
4
denotes a gate insulation film formed on one of principal planes of the silicon substrate
1
by using a silicon oxide film as a material, the reference numeral
5
denotes a gate electrode formed on the gate insulation film
4
by using, as a material, a polycrystalline silicon film doped with phosphorus having a high concentration, the reference numeral
6
denotes a drain region which is formed on one of principal planes
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Cuong Quang
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Thomas Tom
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