Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-05
2002-10-08
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S350000
Reexamination Certificate
active
06462364
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit. Semiconductor integrated circuits according to the present invention can be effectively applied to memories, electronic control units, and processor units that have such-semiconductor integrated circuits as components.
BACKGROUND ART
A method of forming a MOS field effect transistor (hereinafter abbreviated to MOS) in a single crystalline semiconductor layer on an insulator is known as an SOI (Silicon On Insulator) MOS structure (hereinafter abbreviated to SOI.MOS) forming method. The MOS has a thick insulator directly thereunder, and therefore is characterized by its ability to reduce drain junction capacitance and signal line to substrate capacitance to about {fraction (1/10)} of those of conventional MOS. In addition, the MOS is insulated and separated from its supporting substrate, and therefore is also characterized by its ability to substantially eliminate drawback due to irradiation with &agr; rays and latch up phenomena.
Also, as a technique for utilizing the characteristic of SOI.MOS regions of being insulated and separated from each other, there is a method of allowing threshold voltage of SOI.MOS to vary depending on applied gate voltage by electrically connecting a substrate and a gate electrode of the SOI.MOS with each other. This method is proposed in 1994 International Electron Devices Meeting papers p.809 under the title “A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation.” An example of a structure formed by this method is shown in an equivalent circuit diagram of FIG.
2
(
a
) and a plan arrangement view of FIG.
3
. According to the above method, a substrate
3
of SOI.MOS is connected to a gate electrode
6
outside of a channel region by a metallic interconnection
61
via connection holes
112
and
113
. Therefore, body potential rises with increase in applied gate voltage. This results in a forward direction current between a source and a drain, and therefore properties of the transistor exhibit a punch through state, thus resulting in an increase in the current value. In n-channel SOI.MOS, such a state corresponds to a state in which a threshold voltage value is turned negative. When the applied gate voltage is lowered, the body potential decreases. Therefore, the threshold voltage value is turned positive, thus resulting in a decrease in the current value. According to the structure described above, in which the body potential is controlled so as to vary with gate potential, it is possible to achieve properties such that the gradient of dependence of source-drain current on gate voltage is smaller than a gradient value of conventional SOI.MOS. Thus, the structure as described above is characterized by a great current obtained even at a lower supplied voltage than that of a conventional structure.
For the purpose of solving problems with the structure shown in FIG.
2
(
a
), there is proposed a method of inserting a diode between the gate and the substrate. The method is illustrated in FIG.
2
(
b
).
The conventional methods illustrated in FIGS.
2
(
a
) and
2
(
b
) make use of a structure specific to SOI.MOS, in which its body region is completely isolated from the outside, in order to achieve lower operating voltage by controlling the body potential by some method or another. In the case of the structure with its body region completely isolated from the outside, so-called floating body effect is known as the greatest problem with the SOI.MOS. The floating body effect refers to the following phenomena. Minority carriers generated by a strong drain electric field are accumulated in the body because the minority carriers have no path to flow out of the body region. The carriers accumulated in the body cause variations in threshold voltage and also cause abnormal hump properties to appear in current-voltage properties.
According to the above-mentioned method, the body potential is fixed to the gate potential, and therefore the problems of floating body effect are also solved.
In the case of a semiconductor integrated circuit formed on a normal Si substrate, there is also a conceivable system in which well potential is made variable by using a control circuit, so that the threshold voltage value of a transistor in a well region is made variable. According to this system, the threshold voltage values of all transistors in the well region are changed in the same manner.
DISCLOSURE OF INVENTION
A first object of the present invention is to provide SOI.MOS that has variable threshold voltage properties and enables lower voltage operation while ensuring high speed operation.
A second object of the present invention is to solve various problems caused by floating body effect. The various problems caused by floating body effect are the greatest disadvantage of a semiconductor device using an SOI substrate. Specific examples of the problems caused by floating body effect are variations in threshold voltage, appearance of abnormal hump properties in current-voltage properties, and a decrease in source-drain breakdown voltage.
A third object of the present invention is to not only solve the above-mentioned problems but also ensure high density circuit integration.
A fourth object of the present invention is to provide a fabrication method in which the above-mentioned problems are solved by a simpler method.
Background of the objects will hereinafter be described.
The DTMOS mentioned above has a problem in that it is not suitable for greater current and higher speed operation. FIG.
2
(
a
) shows an inverter structure formed by DTMOS techniques. In this structure, application of gate voltage results in a forward direction between a source and a substrate, thereby causing a fatal defect in that a current flows from a gate to the source. In addition, because of the forward direction between the source and the substrate, the gate voltage cannot essentially be raised beyond built-in potential (about 0.6 V) of a source junction. Therefore, when the structure is operated at a supplied voltage of more than 0.6 V, the driving current of the structure becomes lower, rather than greater, than that of a normal structure MOS. Thus, from viewpoints of higher current and higher speed operation, improvements in properties of the structure cannot be expected. This means that the structure will only waste power at a supplied voltage of more than 0.6 V.
FIG.
2
(
b
) shows an example of an inverter in which consideration is given to measures to solve the problems of the DTMOS. In this example, it is possible to apply a gate voltage higher than the built-in potential of a source junction because of the presence of reverse-biased diodes. However, with this system, no effects can be expected from a viewpoint of eliminating floating body effect, which is known as the greatest problem of SOI.MOS. With this structure, it is not possible to extract carriers generated in the body by a strong drain electric field. This means that in the case of n-channel MOS, holes are accumulated in the body, whereas in the case of p-channel MOS, electrons are accumulated. The accumulated carriers cannot be extracted in a connection path to a gate because of the presence of the reverse-biased diodes. Thus, with this structure, it is not possible to solve problems specific to floating body effect such as variations in threshold voltage, decrease in breakdown voltage, and instability in high-frequency operation.
Moreover, the inverter structure shown in FIG.
2
(
b
) has another problem. Specifically, this structure involves complication of circuit design and increase in occupied area, because the structure requires a new periphery circuit for control of transistors MP
1
and MP
2
. When compared with a normal SOI.MOS, the DTMOS structure shown in FIG.
2
(
a
) also has a problem of an additional occupied area for substrate to gate connection outside its channel region. However, the structure of FIG.
2
(
b
) further increases its occupied area, and therefore has a disadvantage of more significantly l
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Nhu David
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