Semiconductor memory having a memory cell array

Details Semiconductor memory having a memory cell array Semiconductor memory having a memory cell array

2001-03-28

2002-10-22

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000

Reexamination Certificate

active

06469335

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a semiconductor memory which has memory cells having capacitors and transistors.
Memories are used to store information in data processing systems. In this case, DRAM (Dynamic Random Access Memory) memories, for example, are used, which usually include a memory cell array and an addressing periphery with logic switching elements. Memory cells including a storage capacitor and a selection transistor are configured in the memory cell array. In this case, the gate of the selection transistor is connected to a word line, the source doping region is connected to the storage capacitor and the drain doping region is connected to a bit line. Application of suitable control voltages to the gate controls the selection transistor in such a way that a current flow between the source and drain regions through the channel of the selection transistor is switched on and off.
Further bit lines are usually configured beside the bit line. The “folded bit line” circuit concept uses two adjacent bit lines which are connected to two inputs of a sense amplifier. In this case, the sense amplifier is usually two interconnected inverters which compare the two adjacent bit lines with one another and evaluate them. The word line runs transversely with respect to the two bit lines and a selection transistor opens when a suitable control voltage is applied to the word line, as a result of which, the charge stored in the storage capacitor flows onto the first bit line. There is no selection transistor configured at the crossover point between the word line and the second bit line and the word line here is referred to as a passing word line. The second bit line serves merely as a reference for the first bit line onto which the charge of the storage capacitor flows. For an adjacent word line, the two bit lines exchange roles, in this case the first bit line serving as an evaluation reference for the memory cell connected to the second bit line. This evaluation principle is very widespread, is used because of its robustness and is described in U.S. Pat. No. 4,443,868 and U.S. Pat. No. 4,807,195. A DRAM memory cell is specified, for example, in U.S. Pat. No. 5,867,420.
Because of the geometrical configuration of the word line and the bit line, which are both dimensioned with the smallest feature size F, the size of a memory cell is always greater than or equal to 8F
2
.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor memory which overcomes the above-mentioned disadvantageous of the prior art apparatus and methods of this general type, and which in particular, has a memory cell size of less than 8F
2
.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory having a memory cell array. The memory cell array includes: a silicon on insulator substrate having an insulation layer; a first memory cell having a first storage capacitor and a first selection transistor formed as an n-channel transistor; and a second memory cell having a second storage capacitor and a second selection transistor formed as a p-channel transistor. The first memory cell and the second memory cell are formed in the silicon on insulator substrate.
The configuration specified uses both n- and p-channel transistors in the memory cell array. In this case, for example, it is provided that one bit line is connected to n-channel transistors and the adjacent bit line is connected to p-channel transistors. The n-channel transistors have the property of turning off for low voltages at the gate and turning on for high voltages. This means that the bit line with the n-channel transistors is active when a high voltage is applied to the word line. In contrast to this, the bit line with the p-channel transistors exhibits an opposite behavior. In this case, the p-channel transistors turn off for a high gate voltage and turn on for a low gate voltage. If a sense amplifier is connected to the bit line with the n-channel transistors and to the bit line with the p-channel transistors and a high word line voltage is applied, then the n-channel transistor opens and the p-channel transistor turns off, with the result that the memory cell—to be read—with the n-channel transistor can be read and the bit line with the p-channel transistors can be used as a reference.
In accordance with an added feature of the invention, at least one of the storage capacitors is a trench capacitor. The design of a storage capacitor as a trench capacitor has the advantage that the storage capacitor can be made in a space-saving manner with a large capacitance. Furthermore, the methods which are usually known for forming trench capacitors can be used.
In accordance with an additional feature of the invention, at least one of the storage capacitors is a stacked capacitor. Stacked capacitors constitute a further possibility for producing the storage capacitor with a large capacitance in a space-saving configuration.
In accordance with another feature of the invention, a trench isolation and the insulation layer insulate the first selection transistor from the second selection transistor. This enables the compact configuration of p-channel transistors and n-channel transistors.
In accordance with an a further feature of the invention, the first selection transistor or the second selection transistor is formed as a vertical transistor. This enables a further compact design for the memory cells and the memory cell array, which enables a memory size of just 4F
2
.
In accordance with a further added feature of the invention, a first bit line is connected to the first memory cell and a second bit line is connected to the second memory cell, and the first bit line and the second bit line are connected to a sense amplifier. Connecting a sense amplifier to the first bit line, which is connected to n-channel transistors, and to the second bit line, which is connected to p-channel transistors, advantageously enables the “folded bit line” concept for memory cell sizes of less than 8F
2
.
In accordance with a further additional feature of the invention, the first selection transistor has a gate made of a mid-gap material which is chosen such that the threshold voltage of the first selection transistor is the negative threshold voltage of the second selection transistor. This enables a symmetrical threshold voltage about the voltage zero for the n-channel transistor and the p-channel transistor.
In accordance with another further feature of the invention, the first selection transistor and the second selection transistor turn off for a first word line voltage. The advantage here is that both the first storage capacitor and the second storage capacitor retain the charge stored in them, since both transistors turn off.
In accordance with another added feature of the invention, the first selection transistor opens for a second word line voltage, which is greater than the first word line voltage. This procedure makes it possible to open the first selection transistor in order to read out the information stored in the first memory cell.
In accordance with another additional feature of the invention, the second selection transistor opens for a third word line voltage, which is less than the first word line voltage. The third word line voltage makes it possible to read out the information stored in the second memory cell.
In accordance with yet an added feature of the invention, polysilicon doped with dopant is used as a gate material for the first selection transistor and/or for the second selection transistor. The threshold voltage of the first selection transistor and of the second selection transistor can be set by way of the doping of the polysilicon. The effect that can thereby be achieved is, for example, that both the first selection transistor and the second selection transistor turn off for the first word line voltage.
In accordance with yet an additional feature of the invention, germanium is used as a d

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