Method of forming package

Details Method of forming package Method of forming package

2000-10-27

2002-10-08

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S617000, C438S108000, C438S613000, C438S109000

Reexamination Certificate

active

06461956

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a wafer. More particularly, the present invention relates to a method of fabricating a direct contact through hole type wafer.
2. Description of the Related Art
A trend for electrical products is to be light, short, small and thin. Not only the chips manufacturing technology but also the packaging technology is developed rapidly to meet the trend. Since a width of a chip is reduced quickly, an integration of the chip is increased and a volume of a chip is decreased. As a result, it is an important task to develop a new packaging technology, which is able to form a small volume package.
Memory modules, for example, are the common semiconductor products. The memory modules are generally formed by the following steps. Chips are first packaged, and then the packages are attached to a printed circuit board. The steps of forming the memory modules are complicated and manufacturing costs are high. Additionally, the arrangement of the packages on the printed circuit board is two-dimensional. An area occupied by the packages is large, so that the packaging density is low. To further reduce reduction of a size of the memory module is limited.
A stacked-type package structure is designed to overcome the above problems. The package structure is three-dimensioinal, thus an area occupied by packages is reduced and the packaging density is increased.
FIG. 1
is a schematic, cross-sectional diagram of a conventional stacked-type package structure.
Referring to
FIG. 1
, chips
10
a
,
10
b
and
10
c
are coupled with leadframes
14
a
,
14
b
and
14
c
by bonding wires
12
, respectively. The chips
10
a
,
10
b
,
10
c
and the leadframes
14
a
,
14
b
,
14
c
are sealed by epoxy
16
to form packages
18
a
,
18
b
and
18
c
The packages
18
a
,
18
b
,
18
c
are stacked and coupled with each other by outer leads of the leadframes
14
a
,
14
b
,
14
c
. Outer leads of the leadframe
14
c
couple with contacts
22
on a printed circuit board
20
by tape automatic bonding.
Although the stacked-type package structure reduces the area occupied by the packages, a height of the stacked-type package structure is high. Furthermore, a signal-transmitting path from the stacked-type package structure to the printed circuit board is long, so that electrical impedance is increased. As a result, signals transmitted decay and are delayed.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of fabricating a direct contact through hole type wafer which fabricates contacts on both sides of a chip.
The invention provides a method of fabricating a direct contact through hole type wafer and fabricateing a wafer-level package, so that a volume and a height of the package are reduced.
The invention provides a method of fabricating a direct contact through hole type wafer that reduces a signal transmitting path and electrical impedance.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides method of fabricating a direct contact through hole type wafer. The method includes the following steps. Devices and contact plugs are formed in one side of a silicon-on-insulator substrate, and multilevel interconnects are formed over the side of the silicon-on-insulator substrate. The multilevel interconnects are coupled with the devices and the contact plugs. Bonding pads which couple with the multilevel interconnects are formed over the multilevel interconnects. An opening is formed on the other side of the silicon-on-insulator substrate to expose the contact plugs. An insulation layer, a barrier layer and a metal layer are formed in sequence in the opening. Bumps are formed on the bonding pads and the metal layer, respectively.
Because a wafer provided according to the invention is a direct contact through hole type wafer, chips are stacked easily and three-dimensionally. A package mounts the chips in a wafer-level package, so that a volume and a height of the package are reduced. Additionally, the signal-transmitting path is reduced. The electrical impedance is also reduced, so that the problem of signals delayed is avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4807021 (1989-02-01), Okumura
patent: 5323060 (1994-06-01), Fogal et al.
patent: 5399898 (1995-03-01), Rostoker
patent: 5728248 (1998-03-01), Weber
patent: 5798014 (1998-08-01), Weber
patent: 5956233 (1999-09-01), Yew et al.
patent: 6020629 (2000-02-01), Farnworth et al.
patent: 6208018 (2001-03-01), Ma et al.
IMB Technical Disclosure Bulletin Mated Array Chip Configuration, vol. 28, No. 2, Jul. 1985, pp. 811-812.*
IMB Technical Disclosure Bulletin Interconnection for Testing Chips/Wafers, vol. 34, No. 7a, Dec. 1991, p. 404.

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