Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-02
2002-10-29
Lam, Tuan T. (Department: 2816)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06473882
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of layout compaction for increasing degree of integration in a semiconductor integrated circuit. This method includes a correction method of mask pattern for modifying in advance a semiconductor mask pattern used for manufacturing semiconductor integrated circuits so that a transfer image close to a desired design pattern can be obtained.
2. Description of the Related Art
Recently, the circuit scale has been increased due to a tendency of multi-functionalization in a semiconductor integrated circuit, accompanying this, the area of a semiconductor integrated circuit has also been increased in proportion to the circuit scale. Whereas, recently, in order to control the manufacturing cost at a low level, restriction of the area to increase is in now rapidly in progress. Further, in order to obtain a high-speed operation, segmentalization in manufacturing process is promptly in progress. To restrict increase of the area as well as to realize a segmentalization in manufacturing process taking account of a required circuit scale and circuit area, it is indispensable to increase the degree of integration at the stage of designing as well as to provide a minute pattern close to the limit of manufacturing ability. Furthermore, when an integrated circuit is manufactured close to the limit of manufacturing ability, an optical proximity effect will appear remarkably.
For a producible layout pattern which is a repetition of an identical pattern or a two-dimensional layout of an identical patter, in order to make the area small, it is indispensable a layout in which the optical proximity effect is taken account of. As for items that have such a layout pattern, a static random access memory, what is called SRAM and a dynamic random access memory, what is call DRAM are typical. In layout in which an identical pattern is disposed repeatedly in all directions such as a SRAM or DRAM, the layout, in which the optical proximity effect is taken account of, can be designed relatively easily.
In this case, it is not always designed with a layout pattern conforming to a process standard but there are many cases where a layout pattern is designed in a dimension smaller than an ordinary process standard.
Whereas, a layout pattern for a circuit that carries out logical operation is designed with a different layout pattern according to respective function. Further, there may be a case where layout patterns disposed on the periphery are different from each other depending on the functions to be provided. Consequently, combinations of them become huge in number. Accordingly, in general, a layout, in which the optical proximity effect is taken account of, is carried out with optical proximity correction by means of a computer-aided design, what is called CAD. An example of the optical proximity correction is disclosed, for example, in Japanese Patent Laid-Open No. 80486/1993. The optical proximity correction is sometimes called OPC for short.
Further, layout compaction also is also carried out by means of the computer-aided design.
FIG. 18
shows a flow of a conventional case where, a layout data of an existing semiconductor integrated circuit is compacted and is converted into a mask pattern.
First of all, a compaction process of a layout data is carried out on the layout data file
11
at the compaction step
12
. The compacted layout data is stored in the layout data file
13
. The compaction process is to compact spaces among polygonal figures contained in a layout data, in some cases, the width of the pattern is also compacted to compact the area of a semiconductor integrated circuit.
In the verification step
14
,the layout data contained in the layout data file
13
is verified whether or not the same conforms to a process standard. Further, in the verification step
14
, it is confirmed whether or not the layout data contained in the layout file
13
is in a conjunction relationship identical as the layout data contained in the layout data file
11
. Still further, in the verification step
14
, a simulation of transistor operation is made to confirm whether or not the circuit operates normally.
In case where the result of the simulation is not correct, the layout data contained in the layout data file
11
is corrected, or the condition of the compaction process executed in the compaction step
12
, and the compaction process is carried out again. In case where the result of the simulation is correct, the layout data file
13
is transferred to the optical proximity correction step
15
. In the optical proximity correction step
15
, after carrying out OPC process appropriate for manufacturing the semiconductor integrated circuit, a mask layout data is generated and is stored in the mask layout data file
16
. The compaction standard for this case is limited to a process standard.
However, in a large-scale semiconductor integrated circuit, not only a repetition of an identical pattern exists such as a SRAM and DRAM, but also a random logic circuit also exists; this random logic circuit will become large in size. Due to this reason, in designing of a semiconductor integrated circuit, it is impossible actually to carry out a layout, in which the optical proximity effect is taken account of, in advance, on respective circuit layouts.
Further, carrying out a layout in which the optical proximity effect is taken account of means that the layout has to be modified when a manufacturing condition of the semiconductor integrated circuit is changed resulting in a layout design poor in production efficiency.
SUMMARY OF THE INVENTION
It is an object of the present invention to carry out layout compaction in which optical proximity effect is taken account of relative to irregularly disposed layout patterns contained within design data of semiconductor integrated circuits. More particularly, it is an object of the invention to provide a method of layout compaction that is capable of increasing the degree of integration of the semiconductor integrated circuit devices.
It is another object of the invention to provide a method of layout compaction that is capable of generating compaction conditions for carrying out a layout compaction process optimized to a manufacturing condition of a semiconductor integrated circuit.
It is still another object of the invention to provide a method of layout compaction that is capable of verifying whether or not any difference is caused in electrical characteristic resulting in a failure in the operation of the semiconductor integrated circuit by carrying out comparison between the result of a layout compaction and the data before the compaction is carried out.
The method of layout compaction according to the invention includes a compaction control step, an optical proximity correction condition generation step (hereinafter, referred to as OPC condition step), a layout compaction step, a first verification step, an optical proximity correction step and a second verification step.
In the compaction control step, a compaction condition appropriate to an input layout pattern is generated.
In the OPC condition generation step, an optical proximity correction condition in which the compaction condition is taken account of generated by the compaction control step.
In the layout compaction step, a compacted layout pattern is generated by carrying out a compaction of the input layout pattern in accordance with the compaction condition.
In the first verification step, the input layout pattern and the compacted layout pattern are received as data and a comparison is made between the input layout pattern and the compacted layout pattern to verify that the compacted layout pattern performs circuit operation properly. In case where any problem is found, a first error data is outputted.
In the optical proximity correction step, an optical proximity effect is corrected in accordance with an optical proximity correction condition relative to the compacted layout pattern, and an optical proximity correct
Lam Tuan T.
Matsushita Electric - Industrial Co., Ltd.
Stevens Davis Miller & Mosher LLP
Tra Quan
LandOfFree
Method of layout compaction does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of layout compaction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of layout compaction will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2982175