Wafer metrology structure

Details Wafer metrology structure Wafer metrology structure

1999-06-24

2002-06-18

Nguyen, Kiet T. (Department: 2881)

Radiant energy

Means to align or position an object relative to a source or...

C257S797000

Reexamination Certificate

active

06407396

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to overlay and critical dimension measurements and, more particularly, to a wafer metrology structure integrating both overlay and critical dimension features. Both overlay and critical dimension data are obtainable within a single scan of a wafer metrology measurement system.
BACKGROUND OF THE INVENTION
The fabrication of many integrated circuits, for example memory devices using large scale integration (LSI) or very large scale integration (VSLI), involves the placement of extremely complex electrical circuits on a single chip of silicon. A photolithography process is frequently used to transfer a microscopic pattern from a photomask to the silicon wafer surface of an integrated circuit. The process involves many iterations of individual reductions. Each individual reduction may introduce errors into the final pattern.
To meet the objective of increasing the density of memory cells or components on a chip, semiconductor processing engineers continue to refine wafer processing methodologies. Of particular importance are the patterning techniques through which individual regions of the semiconductor structure are defined. In an effort to increase the number of components in the semiconductor structure, integrated circuit configurations have evolved into complex, three-dimensional topographies comprised of several layers of material forming patterns overlayed with respect to one another.
As device and memory cell dimensions continue to shrink, the requirement for overlay measurement accuracy continues to increase. Overlay measurement accuracy is required to compensate for processing inaccuracies. Conventional mechanisms used to monitor and correct errors, introduced during the process of transferring a mask pattern from a macroscopic prototype to a microscopic semiconductor chip device pattern, cannot provide the needed resolution and measurement accuracy when implemented with extremely small chip designs.
In the process for forming a semiconductor device on a chip, there are many iterations of transferring an individual pattern from a mask onto the wafer containing the chips. A typical photolithographic system uses a step-and-repeat process to transfer the mask pattern onto the chip. Each successive pattern must be properly aligned to the previously existing patterns. Therefore, each individual pattern transformation may introduce alignment, or overlay, errors. For a pattern formed according to 0.25 &mgr;m design rules, for example, the overlay of one pattern with respect to a pattern formed in a previous level will be in the range of 0.025 &mgr;m. Overlay measurements are critical to semiconductor manufacturing.
Overlay measurements are typically done using optical systems. Consequently, such measurements are susceptible to errors such as lens aberrations of the optical systems. AFM (Atomic Force Microscopy) or SEM (Scanning Electron Microscopy) metrology techniques may be necessary to verify measurement accuracy of optical overlay measurements and to correct for any detectable lens aberrations. A need still exists for improved monitoring and correcting of such errors.
As lithographic feature sizes shrink below 0.2 &mgr;m, additional improvements for overlay measurements are needed to reduce errors. One of the key problems with overlay measurements is the sensitivity to process and exposure tool errors. For example, many types of available measurement targets are sensitive to lens aberrations, such as coma, which produce artificial alignment errors. The measurement errors associated with coma aberrations, or other shortcomings of measurement systems used in a manufacturing environment, will be different for features of different sizes and shapes. Thus, in correcting for a measurement error associated with a 5 micron wide line, for example, a measurement error associated with a 0.5 micron wide line will not be likewise corrected. It is important, therefore, to measure a structure having the same dimension and shape as the critical structure of a given pattern formed within a layer of a device.
FIGS. 1A
,
1
B, and
1
C show conventional designs of alignment target patterns used for optical overlay measurements.
FIGS. 1B and 1C
are taken from U.S. Pat. No. 5,701,013 issued to Hsia et al. There are a number of problems with the alignment targets shown in
FIGS. 1A
,
1
B, and
1
C. First, the design shown in
FIG. 1A
has line widths of 3.0 &mgr;m which are not suitable for critical dimension dispositioning at less than 0.2 &mgr;m ground rules for higher density VLSI devices, due to the problems associated with measurement system errors and the methods for correcting for these errors as discussed above.
Another problem with the
FIG. 1A
design is that control of line width is difficult when the desired device feature is a via-shaped (L=W) pattern. In general, line-space patterns (where L>>W) do not print at the same dose or energy as a via pattern (L=W) and, as noted above, the associated measurement errors will be different for features of different sizes and shapes. Therefore, it is desirable, when making dimension measurements for controlling process dimensions, to have measurement features with a similar (critical) shape to the desired semiconductor feature, as well as a measurement feature of the same dimension. Typically, the overlay measurement feature, such as the one shown in
FIG. 1A
, is made of a much larger dimension and a different shape to avoid dose and dimension sensitivity for printing via structures.
The conventional design shown in
FIG. 1B
also is undesirable in that it is based on a large central feature. This large central feature is known to be sensitive to coma lens aberrations, as discussed above. This sensitivity is manifested as a displacement error, which suggests that alignment errors are present. The alignment errors are actually artificial and result from measurement errors. The
FIG. 1B
design also is unsuitable for controlling dimensional measurements of a trench feature, because the design is sensitive to the distortion associated with filling a trench with material then polishing the trench material using chemical mechanical polishing (CMP) techniques.
The
FIG. 1C
design is undesirable because the additional plurality of features concentrically positioned around the central section also are sensitive to coma aberration. As with the
FIG. 1B
design, the
FIG. 1C
design also is unsuitable for controlling dimensional measurements of a trench feature. The deficiencies described above for conventional techniques, used to measure overlay of one pattern with respect to a previous pattern with optical systems, show that a need still exists for a better and more accurate and efficient technique for carrying out this function.
In addition to the overlay measurements described above, measurements of the critical dimensions of features of patterns formed within each level within a semiconductor device are also made. The critical dimension measurement is commonly made using different features and using different techniques from those used for measuring overlay. It is a common practice to perform separate critical dimension measurements for each pattern formed within a semiconductor device in addition to separate overlay measurements.
To overcome the shortcomings of the overlay measurement techniques currently in use, and to combine the overlay measurement with the critical dimension measurement of two levels performed simultaneously, the present invention is provided.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a wafer metrology structure that overcomes the deficiencies of prior art metrology patterns. To achieve this and other objects, and in view of its purposes, the present invention provides a wafer metrology structure for use in a dimensional analysis of a semiconductor device. The wafer metrology structure includes at least a first feature of a first dimension formed in a first level of the semiconductor device. The firs

Affiliated with

Also associated with

Rating

Wafer metrology structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer metrology structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer metrology structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2980351