Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
1999-05-21
2002-06-18
Kim, Kenneth S. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
C711S149000, C712S200000
Reexamination Certificate
active
06408380
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to a method and apparatus for loading values to registers in a computer processor and, more particularly, to a method and apparatus for loading values to independent registers.
DESCRIPTION OF THE RELATED ART
Conventional computers include a central processing unit (CPU) for executing computer program instructions, a main memory (such as a Random Access Memory (RAM)), and a register file. The main memory includes a plurality of memory locations, each of which is programmable to store a value (also referred to as a “word”) having a fixed number of bits, such as 32 or 64. Memory locations in the main memory are typically used to store executable program instructions and associated data. The CPU executes program instructions stored in the main memory. Each model of CPU recognizes a distinct set of program instructions, referred to as a program instruction set, having predetermined functions and formats. For example, conventional program instruction sets typically include an ADD instruction for adding the values stored in two memory locations. Such an ADD instruction may, for example, consist of three fields: a first field specifying that the instruction is an ADD instruction, a second field specifying the address of the first memory location to add, and a third field specifying the address of the second memory location to add. The three fields of such an ADD instruction are typically stored in three consecutive memory locations in the main memory or within a single memory location.
The register file includes a plurality of registers, which are memory locations, typically located in the CPU, that the CPU can access very quickly compared to accessing the memory locations in the main memory. Program instructions involving registers typically include placing a value (such as a value stored in a memory location) into a specified register (referred to as a “load” operation), copying a value stored in a specified register to a specified memory location (referred to as a “store” operation), and performing arithmetic operations, such as addition and multiplication, on values stored in memory locations and registers.
The speed with which program instructions can be executed by the CPU thus depends, in part, on the speed with which values can be loaded to registers in the register file. Some CPUs attempt to increase load speed by providing a program instruction, referred to as a “load pair” instruction, that allows a pair of values to be loaded to a pair of consecutive registers in the register file. For example, a conventional load pair instruction may specify a source memory location and a target register. Execution of the load pair instruction causes the value in the source memory location to be loaded into the target register, and causes the value in the memory location immediately following the source memory location to be loaded into the register immediately following the target register. In other words, such a load pair instruction causes two consecutive memory locations to be loaded into two consecutive registers. The address of the source memory location is typically required to be an even number.
Conventional load pair instructions, therefore, are limited to loading consecutive registers. This limits the applicability of conventional load pair instructions to situations in which values are to be loaded into consecutive registers. In other situations where two values must be loaded to two registers, a pair of conventional load instructions must be used, thereby losing the advantage of the increased speed provided by use of a load pair instruction.
One environment in which the applicability of conventional load pair instructions is limited is in conjunction with processors which use a special kind of register file referred to as a “rotating register file.” Registers in such a register file do not have fixed numerical identifiers. Rather, the physical registers in a rotating register file are dynamically assigned logical register numbers that may not correspond to the physical locations of the registers in the register file. Programs executing on the processor address registers using their logical register numbers, which the processor converts into physical register numbers that are used to address the register file. In a rotating register file approach, two logically contiguous values cannot be assigned to adjacent register locations. Conventional load pair instructions, as described above, are limited to loading pairs of consecutive registers. It is therefore not possible to use a conventional load pair instruction to load a pair of non-consecutive registers.
The ability to load pairs of non-consecutive registers is particularly useful in certain situations involving rotating register files, such as in compiler optimizations involving software pipelining. For example, rotating register files are sometimes used to speed up the execution of loops having instructions which require multiple cycles for execution. In conventional systems, each iteration of such a loop is delayed by the instruction requiring multiple cycles. Use of a rotating register file permits multiple iterations of the loop to be executed in parallel. When an instruction refers to a register (e.g., R
5
), that register is viewed as a logical register and the corresponding physical register is incremented for each iteration of the loop. Thus, several iterations of the loop may be in progress in different physical registers, and execution of the loop may be operating on physical registers that are not consecutive. It is not possible to load such physically non-consecutive registers using conventional load pair instructions.
SUMMARY
In one aspect, the invention is directed to a computer-readable medium encoded with an instruction for execution by a processor. The instruction comprises an opcode field specifying an instruction to load two independent registers with a first value and a second value; a source field specifying the first value and the second value; a first target register field specifying a first target register to load with the first value; and a second target register field specifying a second target register to load with the second value. In one embodiment the computer-readable medium comprises the memory accessible to the processor. In a further embodiment, the source field specifies an address of a first location in the memory, the first location containing the first value. In yet another embodiment, the address of the first location has a predetermined relationship with an address of a second location in the memory, and the processor is configured to derive the address of the second location from the address of the first location based on the predetermined relationship. In another embodiment the address of the first location and the address of the second location differ by one word. In a further embodiment the opcode field, the source field, the first target register field, and the second target register field comprise bit fields of a single word accessible to the processor. In yet another embodiment the opcode field, the source field, the first target register field, and the second target register field each comprises a word accessible to the processor.
In another aspect, the invention is directed to a method for executing an instruction to load two independent registers with a first value and a second value. The method comprises steps of: (A) receiving an instruction including an opcode field specifying an instruction to load two independent registers with the first value and the second value, a source field specifying the first value and the second value, a first target register field specifying a first target register to load with the first value, and a second target register field specifying a second target register to load with the second value; (B) providing a first target register signal, specifying the first target register, to a first register port address input of a register file; and (C) providing a second target register signal, spec
Colon-Bonet Glenn T.
Fotland David A.
Huck Jerome C.
Karp Alan H.
Mulla Dean A.
Institute for the Development of Emerging Architectures L.L.C.
Kim Kenneth S.
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