Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2000-06-29
2002-11-12
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
Reexamination Certificate
active
06479902
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to deposition of seed layers used in semiconductor processing.
BACKGROUND ART
In the manufacture of integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metallization”, and is performed using a number of different photolithographic and deposition techniques.
In one connection process, which is called a “dual damascene” technique, two channels of conductive materials, are positioned in vertically separated planes perpendicular to each other and interconnected by a vertical “via” at their closest point.
The first channel part of the dual damascene process starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and an optional thin adhesion layer is deposited to coat the walls of the first channel opening to ensure good adhesion and electrical contact of subsequent layers to the underlying semiconductor devices. A barrier layer is then deposited on the adhesion layer improve the formation of subsequently deposited conductive material and to act as a barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices. A first conductive material is then deposited and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel oxide layer and damascenes the first conductive material in the first channel openings to form the first channels.
The via formation step of the dual damascene process starts with the deposition of a thin stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate via areas over the first channels.
A nitride etch is then used to etch out the via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. An adhesion layer is then deposited to coat the via openings and the second channel openings. Next, a barrier layer is deposited on the adhesion layer. This is followed by a deposition of the second conductive material in the second channel openings and the via openings to form the second channel and the via. A second chemical mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by cylindrical vias.
The use of the dual damascene technique eliminates metal etch and dielectric gap fill steps typically used in the metallization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metallization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through dielectrics, such as oxide. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor substrate. To prevent diffusion, materials such as tantalum nitride (TaN), or titanium nitride (TiN) are used as barrier materials for copper. A thin adhesion layer formed of an adhesion material, such as titanium, is first deposited on the dielectrics or vias to ensure good adhesion and good electrical contact of subsequently deposited “barrier” layers to underlying doped regions and/or conductive channels. Adhesion barrier layer stacks formed of adhesion/barrier materials such as tantalum/tantalum nitride (Ta/TaN) and titanium/titanium nitride (Ti/TiN) have been found to be useful as adhesion/barrier material combination for copper interconnects.
After deposition of the barrier layer, a seed layer of conductive material, such as copper, is deposited by an ion metal plasma (IMP) deposition or an electroless plating process. This seed layer is subsequently used as one electrode in an electroplating process which deposits the conductive material which completely fills the channels and vias.
As the size of the channels and vias decrease, it has become increasingly difficult to form a seed layer which is sufficiently thin to provide uniform coverage of the barrier layer but which is thick enough to avoid having openings where the seed layer is not deposited. A solution to this problem has been long sought but has eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides a semiconductor having device interconnects with a catalytic layer deposited in an atomic layer on a barrier layer between the barrier layer and a seed layer on which conductive channel and via material is deposited. The atomic layer provides a high aspect ratio channel and via conformal catalytic layer, which is extremely thin and may be discontinuous.
The present invention provides a semiconductor having device interconnects with a catalytic layer of copper, palladium, nickel, cobalt, silver, or other catalytic material deposited in a atomic layer on a barrier layer of tantalum, titanium, tungsten, their nitrides, or a compound thereof between the barrier layer and a seed layer on which conductive channel and via material is deposited. The atomic layer catalytic material provides good barrier and seed layer adhesion, a strong interface, and enhanced electro migration performance.
The present invention provides a method of manufacturing semiconductor device interconnects with a catalytic layer deposited by atomic layer deposition on a barrier layer. The catalytic layer provides a base for electroless deposition of a conductive seed layer on which conductive channel and via material is deposited by electroplating using the seed layer as an electrode. The atomic layer deposition provides a conformal catalytic layer, which is extremely thin and may be discontinuous, for high aspect ratio channels and vias.
The present invention provides a method of manufacturing semiconductor device interconnects with a catalytic layer of copper, palladium, nickel, cobalt, silver, or other catalytic material deposited by atomic layer deposition on a barrier layer of tantalum, titanium, tungsten, their nitrides, or a compound thereof. The catalytic layer provides a base for electroless deposition of a conductive seed layer on which conductive channel and via material is deposited by electroplating using the seed layer as an electrode. The atomic layer catalytic material provides good barrier and seed layer adhesion, a strong interface, and enhanced electro migration performance.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5169680 (1992-12-01), Ting e
Galewski Carl J.
Lopatin Sergey D.
Advanced Micro Devices , Inc.
Andujar Leonardo
Flynn Nathan J.
Ishimaru Mikio
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