Semiconductor device manufacturing: process – Making field effect device having pair of active regions...
Reexamination Certificate
2000-04-11
2002-06-11
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
C438S241000
Reexamination Certificate
active
06403404
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of forming a semiconductor device, and more particularly to a method of selectively forming a silicide layer only on a logic area of a semiconductor substrate on which the logic area and a memory area are integrated.
A semiconductor memory device is essential for a large scale integrated circuit. The semiconductor memory device is classified into a dynamic random access memory (DRAM) and a static random access memory (SRAM) Those memory devices include many MOS field effect transistors which are advantageous in high density integration. The DRAM is more advantageous than the SRAM in the high density integration to reduce the manufacturing cost, for which reason the DRAM has widely been used in various types storage devices for information devices.
The DRAM store any informations or data by utilizing capacitors provided therein, the informations or data are stored as charges in the capacitors. Realization of the high density integration of the DRAM needs to reduce an occupied area of the storage capacitor over the semiconductor substrate. The reduction in occupied area of the storage capacitor makes it necessary to modify or improve the structure of the storage capacitor in order to keep the capacity.
The DRAM has a memory cell structure having a plurality of cells, each of which comprises a pair of a switching transistor and a capacitor. The switching transistor is provided for selecting the memory cell or controlling input and output of informations into and from the capacitor. This switching transistor comprises the MOS field effect transistor. The DRAM also has a peripheral circuit which performs logic operations to control the memory cells for write operations, read operations and erasing operations. The peripheral circuit comprise logic circuits which further comprise the MOS field effect transistors and complementary MOS field effect transistors. As described above, the DRAM has an integration of the memory cell area having an alignment of the memory cells and the logic area having the logic circuits. In recent years, it is required to integrate the DRAM and a large scale logic device such as a processor over the same semiconductor substrate.
In order to improve a high speed performance of the semiconductor device, it is essential to reduce a sheet resistance and a contact resistance of diffusion layers in an active region of the MOS field effect transistor in the logic area. In order to reduce the sheet resistance and the contact resistance, it is effective to form silicide layers on surfaces of the diffusion layers of the MOS field effect transistors. The memory cell area is quite different from the logic area. The memory cell area needs to prevent any junction leakage current through the diffusion layers of the MOS field effect transistors in the memory cell area, for which purpose no silicide layer is formed over surfaces of the diffusion layers of the MOS field effect transistors. Namely, it is required that the silicide layers are formed on surfaces of the diffusion layers of the MOS field effect transistors provided in the logic area whilst no silicide layers are formed in the memory cell area. Accordingly, it is required to selectively form the silicide layers only in the logic area.
In Japanese laid-open patent publication No. 1-264257, it is disclosed that silicide layers are selectively formed on the logic area of the DRAM.
FIGS. 1A through 1C
are fragmentary cross sectional elevation views illustrative of semiconductor substrates in sequential steps involved in a conventional method of selectively forming silicide layers on a logic area of a DRAM which has an integration of the logic area and a memory cell area.
With reference to
FIG. 1A
, field oxide films
72
as isolations are selectively formed on a surface of a p-type silicon substrate
71
by either a local oxidation of silicon or a shallow trench isolation method, so that the field oxide films
72
define active regions, for example, memory cell regions
80
and logic regions
90
. Gate oxide films
77
are selectively formed on the memory cell regions
80
and the logic regions
90
. Gate electrodes
78
arc formed oil the gate oxide films
77
over the memory cell regions
80
and the logic regions
90
. Silicon nitride films
79
are formed on the gate electrodes
78
. N-
−
type lightly doped regions are formed by self-aligned technique by use of the gate electrodes
78
and the silicon nitride films
79
as masks. Side wall oxide films
81
are formed on side walls of each of the gate electrodes
78
and the silicon nitride films
79
. N-
+
type source and drain regions
73
A and
74
A are selectively formed in the memory cell region
80
by self-aligned technique using the gate electrodes
78
and the silicon nitride films
79
as well as the side wall oxide films
81
as masks, whereby the N-
+
type source and drain regions
73
A and
74
A define N-
−
type lightly doped regions
73
B and
74
B. Also N-
+
type source and drain regions
75
A and
76
A are selectively formed in the logic region
90
by self-aligned technique using the gate electrodes
78
and the silicon nitride films
79
as well as the side wall oxide films
81
as masks, whereby the N−
+
type source and drain regions
75
A and
76
A define N-
−
type lightly doped regions
75
B and
76
B. Namely, source and drain regions
73
and
74
having the lightly doped drain structure are formed in the memory cell region
80
, whilst source and drain regions
75
and
76
having the lightly doped drain structure are formed in the logic region
90
.
With reference to FIG
1
B, a photo-resist film
82
is entirely formed over the memory cell region
80
and the logic region
90
of the p-type silicon substrate
71
. The photo-resist film
82
is then subjected to photo-lithography processes using a photo-mask wherein an exposure and a subsequent development are carried out to selectively remove the photoresist film
82
, so that the logic region
90
is shown. Namely, the gate oxide film
77
, the side wall oxide films
81
and the silicon nitride film
97
are shown. Further, the gate oxide film
77
over the N-
+
type source and drain regions
75
A and
76
A is removed, so that the N-
+
type source and drain regions
75
A and
76
A are shown. The silicon nitride film
79
is also removed so that the gate electrode
78
is shown.
With reference to
FIG. 1C
, a refractory metal film is entirely deposited by a sputtering method, so that the refractory metal film extends over the photo-resist film
82
and over the N-
+
type source and drain regions
75
A and
76
A, the side wall oxide films
81
and the gate electrode
78
. The refractory metal film may be made of a refractory metal such as tungsten, molybdenum, and titanium. The substrate
71
is then subjected to a heat treatment to cause silicidation reaction between refractory metal in the refractory metal film and silicon in the N-
+
type source and drain regions
75
A and
76
A and the gate electrode
78
, thereby forming silicide layers
83
over the N-
+
type source and drain regions
75
A and
76
A and the gate electrode
78
. Unreacted refractory metal film remain over the side wall oxide films
81
and the photo-resist film
82
. The unreacted refractory metal film is removed by an etching process.
As described above, the conventional method selectively forms the silicide layers only on the logic region
90
. It is also possible to form the CMOS transistor in the logic region
90
if necessary.
The above described conventional method has the following problems. It is required to carry out an additional photo-lithography process whereby the gate oxide film
77
selectively removed and the silicon nitride film
79
is removed, so that the N-
+
type source and drain regions
75
A and
76
A as well as the gate electrode
78
are shown before the refractory metal film is deposited. This additional photo-lithography process results in increase
Dang Phuc T.
Nelms David
Young & Thompson
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