Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-04-25

2002-02-12

Nelms, David (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C257S903000, C257S368000

Reexamination Certificate

active

06347048

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor memory device such as a static random access memory (SRAM).
BACKGROUND
An SRAM, which is one type of semiconductor memory device, does not need refreshing. Therefore, the SRAM enables the system configuration to be simplified and consumes only a small amount of electric power. Because of this, the SRAM is suitably used as a memory for portable devices such as portable telephones.
There has been a demand for miniaturization of portable devices. To deal with this demand, the memory cell size of the SRAM must be reduced.
SUMMARY
An objective of certain embodiments of the present invention is to provide a semiconductor memory device having memory cells of a reduced size.
According to one embodiment of the present invention, there is provided a semiconductor memory device comprising:
a memory cell which includes a first driver transistor, a second driver transistor, a first load transistor, a second load transistor, a first transfer transistor, and a second transfer transistor, wherein:
the memory cell has first and second gate electrode layers, first and second drain-drain connecting layers, first and second drain-gate connecting layers, and a source contact layer;
the first gate electrode layer includes a gate electrode of the first driver transistor and a gate electrode of the first load transistor;
the second gate electrode layer includes a gate electrode of the second driver transistor and a gate electrode of the second load transistor;
a source region of the first and second driver transistors is located in a region between the first and second gate electrode layers;
the source contact layer is located in the region between the first and second gate electrode layers;
the first and second drain-drain connecting layers are located higher than the first and second gate electrode layers;
the first and second gate electrode layers are located between the first and second drain-drain connecting layers;
the first drain-drain connecting layer connects a drain region of the first driver transistor to a drain region of the first load transistor;
the second drain-drain connecting layer connects a drain region of the second driver transistor to a drain region of the second load transistor;
the first and second drain-gate connecting layers are located higher than the first and second gate electrode layers;
the first and second drain-gate connecting layers are located in a different layer from the first and second drain-drain connecting layers;
the first drain-gate connecting layer connects the first drain-drain connecting layer to the second gate electrode layer; and
the second drain-gate connecting layer connects the second drain-drain connecting layer to the first gate electrode layer.
The semiconductor memory device according to this embodiment of the present invention includes the gate electrode layers which become gates of inverters, the drain-drain connecting layers for connecting drains of the inverters, and the drain-gate connecting layers for connecting the gate of one inverter to the drain of the other inverter. In this semiconductor memory device, a flip-flop is formed of three layers (gate electrode layer, drain-drain connecting layer, and drain-gate connecting layer). Therefore, the pattern of each layer can be simplified (linear pattern, for example) in comparison with the case of forming a flip-flop of two layers. According to this semiconductor memory device, since the pattern of each layer can be thus simplified, a semiconductor memory device with a memory cell size of 4.5 &mgr;m
2
or less can be fabricated, for example.
According to this semiconductor memory device, the first gate and second gate electrode layers are located between the first drain-drain connecting layer and the second drain-drain connecting layer. Therefore, the source contact layer of the driver transistors can be disposed at the center of the memory cell. Moreover, a wiring layer which is formed in the same layer as the drain-drain connecting layer and to which the source contact layer is connected can be disposed at the center of the memory cell. This increases the degree of freedom relating to the formation of the first and second drain-gate connecting layers, whereby the memory cell size can be reduced. In the present invention, the source contact layer is a conductive layer used to connect the source region of the driver transistor to the wiring layer.
According to this semiconductor memory device, the drain-gate connecting layers are located higher than the gate electrode layers and the drain-drain connecting layers. Therefore, the source contact layer can be located in the region between gate electrode layers (or region between the first gate electrode layer and second gate electrode layer) while preventing the drain-gate connecting layer from coming in contact with the source contact layer. Therefore, parasitic resistance of the driver transistors can be decreased. Moreover, the pattern of the source region can be simplified (for example, a pattern with a uniform width such as an approximately linear pattern or rectangular pattern), whereby reproducibility of the pattern of the source region can be improved in a photolithography process. This increases dimensional accuracy of the channel width of the driver transistors, whereby the operation of the memory cell can be stabilized.
In this semiconductor memory device, the width of the source region may be approximately uniform.
The source contact layer may be located in the source region.
This semiconductor memory device may further comprise a word line, wherein: the word line is located on the side of the first and second driver transistors; the word line includes gate electrodes of the first and second transfer transistors; and the word line has a linear pattern.
According to this configuration, since the pattern of the word line is linear, the length of the word line can be decreased in comparison with a word line having a partly curved pattern. Therefore, according to this configuration, the resistance of the word line can be decreased. The width of a word line having a partly curved pattern tends to be decreased at the curved section. This causes the narrow line effect of silicide to occur in a salicide of the word line, whereby the resistance of the word line locally increases. According to this configuration, since the pattern of the word line is linear and does not have a curved section, occurrence of the narrow line effect of silicide caused by the curved section can be prevented, thereby preventing a local increase in the resistance of the word line due to the narrow line effect of silicide.
This semiconductor memory device may further comprise:
another memory cell which includes a third transfer transistor and a fourth transfer transistor;
first and second bit lines;
another word line; and
a well contact region, wherein:
the other memory cell is located adjacent to the memory cell;
the first and third transfer transistors use in common a first source/drain region to which the first bit line is connected;
the second and fourth transfer transistors use in common a second source/drain region to which the second bit line is connected;
the other word line includes gate electrodes of the third and fourth transfer transistors;
the other word line has a linear pattern;
the well contact region is located between the word line and the other word line; and
the memory cell and the other memory cell uses in common the well contact region.
According to this configuration, since the above word line and the other word line have a linear pattern, the well contact region can be located between the above word line and the other word line without increasing the memory cell area. Therefore, the size of the semiconductor memory device can be reduced.
According to this configuration, occurrence of latchup in the semiconductor memory device can be prevented. The reasons therefor are described below. Generally, when drain current flows by operating a transistor, substrate current (current from e

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