Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-08
2002-10-01
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C365S145000, C365S065000, C365S182000, C365S184000
Reexamination Certificate
active
06459110
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor storage element provided with a ferroelectric capacitor.
2. Description of the Related Art
Ferroelectrics exhibit spontaneous polarization, which reverses direction in response to an applied field. There are two principal types of semiconductor storage element that make use of this spontaneous polarization. The first type is called the one-transistor type, and the second type is called the one-transistor-one-capacitor type. Recently, as non-destructive data reading and high-level integration have become possible, there has been demand for implementation of the one-transistor type.
Examples of one-transistor type semiconductor storage elements are presented in documents such as
Technical Report of IEICE SDM
93-136, pp. 53-59. According to the MFMIS structure (Metal/Ferroelectric/Metal/Insulator/Semiconductor) presented in that document, an insulating layer, a lower electrode, a ferroelectric layer and an upper electrode are sequentially laid on a semiconductor substrate. The reason for this structure is that ferroelectric layers do not grow well on semiconductors and insulating layers. In the MFMIS structure, it is sufficient that the ferroelectric layer is formed above the conductive material (i.e., metal) layer. Thus, layer formation is easy.
Further, when a voltage is applied to the ferroelectric layer, charge is accumulated at the ferroelectric layer by remanence of the ferroelectric layer. Specifically, when a positive voltage is applied to the ferroelectric layer, a positive charge is accumulated, and when a negative voltage is applied to the ferroelectric layer, a negative charge is accumulated. In an MFMIS structure semiconductor storage element, the accumulated charge excites a charge at the top surface of the substrate. Hence, even when the applied voltage is 0V, a switching state of a transistor, which is one of an ON state and an OFF state, is selectively preserved. In this way, data can be written at the ferroelectric layer. Moreover, current between a source electrode and a drain electrode changes in response to the switching state of the transistor. Thus, by detection of this change, data reading can be performed.
However, when data is written to a selected cell in a memory cell structure that uses conventional semiconductor storage elements, disturbance, which is alteration of data stored in other cells, may occur. An example is described with reference to
FIG. 4
, which is a circuit diagram showing the structure of a memory array using conventional semiconductor storage elements.
As shown in
FIG. 4
, the memory array is formed with a predetermined number of memory cells lined up horizontally and vertically. Each memory cell is an MFMIS structure combining a ferroelectric capacitor and a p-type control transistor. Namely, each memory cell has a structure wherein one electrode of the ferroelectric capacitor (the lower electrode) is connected with a gate electrode of the control transistor.
Further, a line Wn (the symbol n represents a row number of a specified memory cell) is connected at another electrode of the ferroelectric capacitor (the upper electrode). A line Bn is connected at the source electrode of the control transistor, and a line Dm (the symbol m represents a column number of the specified memory cell) is connected at a drain electrode of the control transistor. Further, the drain electrode of the control transistor is connected to the substrate.
Next, using a memory cell
100
in the memory array shown in
FIG. 4
as an example, operation of the memory cells is explained. The upper electrode of the ferroelectric capacitor of the memory cell
100
is connected with line W
2
, and the drain electrode of the control transistor of the memory cell
100
is connected with line D
2
.
To record data at the memory cell
100
, a voltage is applied to line W
2
. This voltage is set to be large enough to reverse the polarization of the ferroelectric capacitor. In this example, the voltage is set at 10V. Meanwhile, line D
2
stays at 0V. When voltage is applied thus, data is written at the memory cell
100
.
Further, when memory cell
100
is being written to, voltages of 5V are applied to lines Wn and Dm that are connected to other memory cells, in order to protect data. Hence, when data is written to memory cell
100
in this way, a 5V voltage difference occurs between the substrate and upper electrodes of ferroelectric capacitors of memory cells, besides memory cell
100
, that are connected to one of lines D
2
and W
2
. Consequently, data stored at these memory cells may be destroyed.
For example, at a memory cell
102
, whose ferroelectric capacitor upper electrode is connected with line W
3
and whose control transistor drain electrode is connected with line D
2
, a datum −Pr has been stored (the symbol Pr represents a remanence value).
FIG. 5
is a graph showing a hysteresis characteristic of a ferroelectric capacitor. The horizontal axis of the graph is applied voltage and the vertical axis is polarization charge. As shown by hysteresis curve a, when a voltage of about 5V (hereinafter called the reversal voltage) is applied to the ferroelectric capacitor, the ferroelectric remanence changes from −Pr to +Pr.
As described above, during operation of the memory cell array, a 5V voltage difference occurs at memory cell
102
, between the ferroelectric capacitor upper electrode and the substrate. If the aforementioned reversal voltage is larger than 5V, the stored data state returns to the original value, −Pr, after the applied voltage is removed. However, because of variations in ferroelectric characteristics and voltage levels, the applied voltage may be larger than 5V or the reversal voltage may be smaller than 5V. In such cases, the datum may change from −Pr to +Pr and a data error may occur.
SUMMARY OF THE INVENTION
Therefore, realization of a semiconductor storage element in which a voltage capable of reversing polarization is applied only to a memory cell that is an object of data writing has been conventionally desired.
A first aspect of a semiconductor storage element of the present invention comprises: a ferroelectric capacitor; a selection transistor; and a control transistor. One electrode of the ferroelectric capacitor is connected with a first main electrode of the selection transistor, and a second main electrode of the selection transistor is connected with a control electrode of the control transistor.
A second aspect of a semiconductor storage element of the present invention comprises: a ferroelectric capacitor; a first transistor; and a second transistor. One electrode of two electrodes of the ferroelectric capacitor is connected with one electrode of two main electrodes of the first transistor, and another main electrode of the first transistor is connected with a control electrode of the second transistor.
In the semiconductor storage element of the second aspect, the first transistor may be a field effect transistor, with the two main electrodes of the first transistor being a source electrode and a drain electrode.
Also, in the semiconductor storage element of the second aspect, the second transistor may be a field effect transistor, with the control electrode of the second transistor being a gate electrode.
A third aspect of a semiconductor storage element of the present invention comprises: a ferroelectric capacitor structured to have a ferroelectric layer between an upper electrode and a lower electrode; a selection transistor having a first main electrode, a second main electrode and a control electrode; and a control transistor having a first main electrode, a second main electrode and a control electrode. The lower electrode of the ferroelectric capacitor is connected with the first main electrode of the selection transistor, and the second main electrode of the selection transistor is connected with the control electrode of the control transistor.
A memory cell array of the present invention compr
Burdett James R.
Lee Eddie
Nguyen Joseph
Oki Electric Industry Co. Ltd.
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