Semiconductor device manufacturing: process – Chemical etching – Altering etchability of substrate region by compositional or...
Reexamination Certificate
2001-06-29
2002-10-29
Goudreau, George (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Altering etchability of substrate region by compositional or...
C438S301000, C438S303000, C438S305000, C438S308000, C438S953000, C438S753000, C438S704000, C438S723000, C438S696000, C134S001300
Reexamination Certificate
active
06472328
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to methods of forming electrical contacts to semiconductive material.
BACKGROUND OF THE INVENTION
In semiconductor circuitry fabrication, electrical connections or contacts are commonly made between conductive lines and conductive diffusion areas formed within a semiconductive substrate. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Such electrical contacts are typically accomplished by initially etching a contact opening through insulative material over a conductive diffusion region comprising highly doped semiconductive material to which electrical connection is desired. Conductive material, such as conductively doped semiconductive material, is thereafter formed within the contact opening in electrical connection with the diffusion region within the semiconductive substrate. The conductive contact filling material can then either be planarized or, if deposited to a sufficient thickness, patterned into a conductive line or other desired electronic component.
One problem associated with such connections is exemplified in FIG.
1
. There illustrated is a semiconductor wafer fragment
10
comprised of a p- doped monocrystalline silicon substrate having a pair of conductive gate lines
14
and
16
formed thereover. Source/drain diffusion regions
18
,
20
, and
22
, constituting n+ dopant, are formed within substrate
12
to form field effect transistors. In this example, ii electrical connection with an overlying conductive line is desired to be made with respect to diffusion region
20
.
An insulating layer
24
is formed over substrate
12
and gates
14
and
16
, and is subsequently planarized. A contact opening
26
is then patterned and formed, typically by dry etching, through insulating layer
24
over diffusion region
20
. Such has the effect of roughening or otherwise damaging the outer surface of silicon substrate
12
within diffusion region
20
upon outward exposure thereof. This also undesirably has a tendency to change an outer portion
28
of the semiconductive material of substrate
12
exposed by the contact etching. This change typically manifests itself in a modified crystalline structure of the silicon material of substrate
12
. Subsequently, a buried contact ion implant region
30
is formed into and through region
28
within diffusion region
20
. Implant
30
is provided to achieve enhanced electrical contact between diffusion region
20
and a subsequently deposited conductive material. The substrate is typically subjected to an anneal in an attempt to repair or overcome the silicon damage caused by both the dry etch forming contact opening
26
and that caused by the implant to form region
30
.
The wafer is subjected to an HF clean for a short period of time to clear any native oxide formed over region
20
. A conductive layer
32
is then formed within contact opening
26
and over insulating layer
24
, for example by depositing or otherwise forming a conductively doped semiconductive material such as polysilicon.
Unfortunately, the combined effect of both the changed outer portion
28
from the dry etch and the subsequent implant region
30
, even with a subsequent anneal, forms a less than desired electrical connection between the diffusion region and conductive material
32
, particularly where the conductive material within contact opening
26
is essentially void of any silicide material. It would be desirable to overcome some of these drawbacks associated with forming electrical contacts to semiconductive material.
SUMMARY OF INVENTION
In one aspect of the invention, a method of forming an electrical contact to semiconductive material includes forming an insulative layer over a contact area of semiconductive material. A contact opening is etched through the insulative layer to the semiconductive material contact area. Such etching changes an outer portion of the semiconductive material exposed by the etching. The change is typically in the form of modifying crystalline structure of only an outer portion from that existing prior to the etch. The changed outer portion of the semiconductive material is etched substantially selective relative to semiconductive material therebeneath which is unchanged. The preferred etching: chemistry is a tetramethyl ammonium hydroxide solution. A conductive material within the contact opening is formed in electrical connection with the semiconductive material.
Is In another implementation, the changed outer portion is etched with a basic solution regardless of selectivity in the etch relative to semiconductive material therebeneath which is unchanged.
The preferred conductive material is conductively doped semiconductive material which is formed in the contact opening to be in contact with semiconductive material which is unchanged. Further, the conductive material within the contact opening is preferably void of any silicide material.
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patent: 4704783 (1987-11-01), Possin
patent: 4978418 (1990-12-01), Arnold, Jr. et al.
patent: 5441599 (1995-08-01), Reinhardt
patent: 5702983 (1997-12-01), Mathews et al.
patent: 5827784 (1998-10-01), Locos
patent: 5932912 (1999-08-01), Horita et al.
patent: 6281131 (2001-08-01), Gilton et al.
patent: 02-232925 (1989-03-01), None
patent: 02-295131 (1990-12-01), None
patent: 08-046209 (1996-02-01), None
patent: 09-074196 (1997-03-01), None
Gilton Terry
Kurth Casey
Meyer Russ
Wald Phillip G.
Goudreau George
Micro)n Technology, Inc.
Wells St. John P. S.
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