Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-10-31
2002-08-06
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257S374000
Reexamination Certificate
active
06429477
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates, in general, to the design and production of semiconductor microchips. More particularly, this invention relates to methods for electrically connecting the various components of a semiconductor microchip.
2. Background Art
The advent of the microchip has revolutionized life in the latter half of the 20th century. Microchips are a ubiquitous part of life, being found in everything from computers to garage door openers. Over the years, the microelectronics industry has diligently sought to further reduce the size of the microelectronics built on silicon chips.
One of the major factors in determining the degree of miniaturization possible on a chip is the amount and type of connections required between the electrical devices contained on the chip. For example, contact needs to be made between devices such as transistors, and wiring levels above the transistors. This has typically been accomplished through the formation of “vertical interconnects” (commonly called studs) that are formed to connect the underlying device with the overlying wiring. For example, using a “damascene” process “troughs” and “vias” are etched in the silicon dioxide between circuit devices. The entire surface of the chip is then covered with copper or aluminum. Next, the copper is planarized, removing it from the chip's surface and leaving copper only in the troughs and vias. The remaining copper in the troughs forms the “wires” that provide intralevel connection while the copper in the vias forms the vertical interconnect studs that provide interlevel connection.
In recent years, a new type of semiconductor processing has become important. This process, called silicon-on-insulator, or SOI, uses a buried insulator layer formed in the wafer. Devices such as transistors are then formed in the silicon layer above insulator. SOI wafer structures provide many advantages, particularly for high performance, low-voltage devices. For example, advantages of SOI include improved performance at low voltages resulting from reduced junction capacitances, and dynamic threshold voltages effects, and reduced soft-error upset rate due to decreased silicon collection volume
On issue in SOI processing is the need for selective body contacts between the SOI layer, the layer of silicon formed on the insulator, and the substrate layer formed beneath the insulator layer. For example, in some applications body contacts are needed to provide a conduction path for rapid equilibration of body charge. In this case, the body contact helps avoid instabilities that can result from transient operations. This use of body contacts are particularly important in those application that require closely matched electrical characteristics of adjacent devices, such as cross-coupled pairs in sense amps, SRAM cells, current mirrors, etc.
Accordingly, the need exists for vertical interconnects and body contacts that provide necessary connections in SOI devices while minimizing the space and processing complexity required for these contacts.
DISCLOSURE OF INVENTION
The present invention overcomes the difficulties found in the background art by providing a body contact and diffusion contact formed in a single shared via for silicon on insulator (SOI) technologies. By forming the body contact and diffusion contact in a single shared via, device size is minimized and performance is improved. Particularly, the formed body contact connects the SOI layer with the underlying substrate to avoid instabilities and leakage resulting from a floating SOI channel region. The formed diffusion contact connects device diffusions to above wiring to facilitate device operation. By providing the body contact and diffusion contact together in a single shared via, the preferred embodiment avoids the area penalty that would result from separate contacts. Additionally, the preferred embodiment provides a body contact that is self aligned with other devices, minimizing tolerances needed while minimizing process complexity. Additionally, the shared via body contact and diffusion contact can be selectively formed borderless to adjacent gate conductors in the device.
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Divakaruni Rama
Mandelman Jack A.
Tonti William R.
Nguyen Cuong Quang
Schmeiser Olsen & Watts
Thomas Tom
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