Static information storage and retrieval – Read/write circuit – Serial read/write
Reexamination Certificate
2000-11-01
2002-12-31
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Serial read/write
C365S230010, C365S239000, C365S189050, C365S222000, C365S230030
Reexamination Certificate
active
06501698
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
A method and device for providing increased access speed to a DRAM array-based memory device, and more particularly to a DRAM array-based memory device including a data transfer area that accelerates read and write requests.
2. Discussion of the Background
A variety of memory devices are presently available with varying physical characteristics. Dynamic Random Access Memory (DRAM) has the advantage that the number of gates per cell is small and the density is generally quite high. On the other hand, DRAM is disadvantageously prone to data loss if the individual rows of data are not periodically refreshed. Accordingly, known systems have used external or internal refresh circuitry to prevent data loss. External circuitry complicates the design of an external memory controller and may therefore be disadvantageous. DRAMs disadvantageously have relatively long access times as compared to other memory devices (e.g., static memories) and therefore may act as a bottleneck for a processor that requests memory accesses more quickly than the DRAM can sustain.
As an alternative, Static Random Access Memory (SRAM) devices utilize a greater number of transistors per memory cell and, as a result, do not require refreshing. Moreover, the transistor interconnections allow data to be read from and written to the device significantly more quickly than DRAMs. Unfortunately, the cost of SRAMs per bit is significantly more expensive than the cost of DRAMs per bit. Accordingly, it is often prohibitively expensive to use SRAM for a computer's main memory, and instead a relatively small amount of SRAM cache is often used only between the processor and a larger amount of DRAM.
As an alternative to both DRAM and SRAM designs, hybrid memories have been introduced that have some of the characteristics of both DRAM devices and SRAM devices. One such device is known as an “Enhanced DRAM” (EDRAM) and is described in U.S. Pat. Nos. 5,887,272, 5,721,862, and 5,699,317 (hereinafter “the '272 patent,” “the '862 patent”, and “the '317 patent,” respectively), each naming Sartore et al. as inventors. (Those patents also are assigned to the assignee of the present invention and incorporated herein by reference.) The EDRAM devices disclosed therein provide increased data throughput by providing at least one higher speed storage area (as compared to the DRAM sub-array), storing at least a portion of a row, associated with each DRAM sub-array or with each group (e.g., pair) of DRAM sub-arrays.
Another hybrid memory device, that provides double buffering for writes, is described in U.S. Pat. No. 5,784,705 (hereinafter “the '705 patent”) to Leung, assigned at the time of issue to MoSys, Inc., of Sunnyvale, Calif., and incorporated herein by reference. The abstract of the '705 patent discloses that its memory architecture uses a write buffer that is a “two entry write buffer in a first in, first out manner.” FIG. 7 of the '705 patent illustrates a double buffering circuit.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a structure and method for hiding DRAM cycle time behind a burst write access.
It is a further object of the present invention to provide a structure and method for hiding DRAM cycle time behind both burst write accesses and burst read accesses.
These objects and other advantages are made possible by using read and write data transfer areas in an augmented Dynamic Random Access Memory (DRAM) device. By providing fast write access to the write data transfer areas, burst writes can be completed at SRAM-like write speeds. The contents of the write data transfer areas are then later retired to the DRAM memory array at speeds compatible with the underlying DRAM array.
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Elms Richard
Enhanced Memory Systems Inc.
Hogan & Hartson LLP
Kubida, Esq. William J.
Meza, Esq. Peter J.
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