Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2000-12-26
2002-08-20
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S009000, C326S021000
Reexamination Certificate
active
06437601
ABSTRACT:
This application is related to U.S. patent application entitled, “Data and Strobe Repeater Having a Frequency Control Unit to Re-time the Data and Reject Delay Variation in the Strobe” of Borkar et al., filed on the same date as this application and assigned to the same assignee.
BACKGROUND
This invention is generally related to clock synchronization in digital electronic systems, and more particularly to the use of timing strobes for synchronizing an on-chip clock and validating the application of the clock.
When communicating data, such as digital memory content, memory addresses, and/or control bits, from one device to several others in a digital logic system, it is necessary to insure that each receiver device captures the actual data that has been transmitted. This is very difficult to guarantee, particularly in high speed systems that process and transmit at several hundred megabits per second or higher, because of delays and other impairments to which a signal that carries the data is subjected while it is traveling between the transmitter and the receiver on a printed wiring board.
What has been conventionally done to alleviate this problem is to attempt to synchronize the transmitter and the receivers. Ideally, when synchronized, the transmitter and the receivers would process, generate, and capture data at a constant frequency defined by a free-running periodic clock signal that has been distributed to them. However, in practice, the devices must be designed to tolerate some unavoidable variation in the frequency that is derived by each device from the received clock signal. This variation, known as cycle to cycle jitter, may be caused by a number of factors, such as transmission line effects on the printed wiring board. The jitter becomes much more difficult to tolerate by the system as the clock frequency, and hence the performance of the system, increases. In some high performance systems, it may be expected that the clock jitter simply cannot be tolerated, such that the only solution would be to reduce the clock frequency.
REFERENCES:
patent: 5452323 (1995-09-01), Rosen
patent: 5578946 (1996-11-01), Cargerry et al.
patent: 5857005 (1999-01-01), Buckenmair
Borkar Shekhar Y.
Haycock Matthew B.
Kennedy Joseph T.
Martin Aaron K.
Mooney Stephen R.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Tokar Michael
Tran Anh Q.
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