Method of making chip scale package

Details Method of making chip scale package Method of making chip scale package

2000-07-06

2002-02-19

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S108000, C438S124000, C438S126000, C438S127000, C438S614000

Reexamination Certificate

active

06348399

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of making a chip scale package, and more specifically to a method of making a molded chip scale package with a flip-chip configuration.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the velocity and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher package efficiency. Demand for miniaturization is the primary catalyst driving the usage of advanced packages such as chip scale packages (CSP) and flip chips. Both of them greatly reduce the amount of board real estate required when compared to the alternative ball grid array (BGA) and thin small outline package (TSOP). Typically, a CSP is 20 percent larger than the chip itself. The most obvious advantage of CSP is the size of the package; that is, the package is slightly larger than the chip. Another advantage of CSP is that the package facilitates test and burn-in before assembly as an alternative to known good die (KGD) testing. In addition, CSP can combine many of the benefits of surface mount technology (SMT), such as standardization, encapsulation, surface mount, and reworkability, with the benefits of flip chip technology, such as low inductance, high I/O count, and direct thermal path.
However, CSP has at least one disadvantage compared to conventional BGA and TSOP, namely, high cost per unit. However, this problem could be eliminated if chip-sized packages could be mass produced more easily. Therefore, there is a need in the semiconductor packaging industry for CSP using mass production techniques at the wafer-level, as is illustrated in U.S. Pat. No. 5,323,051, U.S. Pat. No. 5,925,936 and U.S. Pat. No. 6,004,867.
Disclosed in the technical article by Baba et al. titled, “Molded Chip Scale Package for High Pin Count,” Proceedings of the 46th ECTC, Orlando, Fla., 1996, pp. 1251-1257, is a process for making a CSP
100
(see
FIG. 4
) which is shown in greater detail in FIG.
5
. As shown in
FIG. 1
, the IC chip
10
has a plurality of rerouted under bump metallurgy (UBM)
12
electrically connected to bonding pads on its active surface. First, copper lands
22
and inner solder bumps
24
are formed on a base frame
20
made of ferroalloy. The copper lands
22
are formed by plating and the inner solder bumps
24
are formed onto the copper lands
22
by stencil printing. Then, the chip
10
is attached onto the inner solder bumps
24
of the base frame
20
, using flip chip bonding technology. Second, as shown in
FIG. 2
, the bonded chip
10
and portions of the frame
20
are encapsulated with a package body
30
by a molding process identical to that used in conventional molding of IC packages. Third, as shown in
FIG. 3
, the base frame
20
is separated from the encapsulated chip
10
in a way that transfers the copper lands
22
and the inner solder bumps
24
from the base frame
20
to the chip
10
. Finally, as shown in
FIG. 4
, solder balls
40
are attached to the exposed surfaces of the transferred copper lands
22
.
FIG. 5
shows in greater detail the chip
10
with an external solder ball
40
. The chip
10
has a bonding pad
12
formed on its active surface. The bonding pad
12
and the external solder ball
40
are connected through wiring conductor pattern
50
, UBM
12
, inner solder bump
24
and transferred copper land
22
. The package body
30
is capable of providing stress relief in the solder joints due to CTE mismatch between chip and substrate. The CSP shown in
FIG. 4
has advantages of compact package size, good electrical performance, and high reliability. However, as can be appreciated from the above prior art processes, the method of making CSP
100
is rather complex and costly.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to overcome, or at least reduce the problems and disadvantages associated with the above-described technique for fabricating a molded chip scale package.
It is a further objective of the present invention to provide a simplified method which can be used to produce a molded chip scale package.
The method of making a chip scale package in accordance with the present invention comprising the following steps: (a) providing a semiconductor chip having a plurality of metal bumps formed on the active surface thereof; (b) providing a metal plate having a plurality of flip-chip pads formed on a surface thereof; (c) positioning the semiconductor chip on the surface of the metal plate with the metal bumps on the chip aligned with the flip-chip pads on the metal plate; (d) connecting the metal bumps on the active surface of the semiconductor chip to the flip-chip pads on the surface of the metal plate; (e) encapsulating the semiconductor chip against a portion of the surface of the metal plate; (f) removing the metal plate while leaving the flip-chip pads intact; and (g) forming a plurality of solder balls on the flip-chip pads.
Using the technique of the present invention, it becomes possible that the manufacture of a molded chip scale package can be relatively simplified and economical, yet highly reliable.


REFERENCES:
patent: 5323051 (1994-06-01), Adams et al.
patent: 5620928 (1997-04-01), Lee et al.
patent: 5656550 (1997-08-01), Tsuji et al.
patent: 5830800 (1998-11-01), Lin
patent: 5925936 (1999-07-01), Yamaji
patent: 5930603 (1999-07-01), Tsuji et al.
patent: 6004867 (1999-12-01), Kim et al.
patent: 6204559 (2001-03-01), Lin et al.
patent: 6238952 (2001-05-01), Lin
Molded Chip Scale Package for High Pin Count (1996 Electronic Components and Technology Conference) by Shinji Baba et al., pp. 1251-1257.

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