DRAM refresh timing adjustment device, system and method

Details DRAM refresh timing adjustment device, system and method DRAM refresh timing adjustment device, system and method

2001-07-06

2002-08-20

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S211000

Reexamination Certificate

active

06438057

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to devices, systems, and/or methods for refreshing the contents of a dynamic random access memory (DRAM) array and, more particularly, to devices, systems, and/or methods for utilizing a temperature of the DRAM array to adjust a refresh rate at which the contents of the DRAM array are updated.
A common form of random access memory (RAM) is dynamic random access memory (DRAM). With reference to the equivalent circuit shown in
FIG. 1
, DRAMs employ a semiconductor technology called complementary metal-oxide-semiconductor CMOS to implement a memory array
10
including a plurality of memory cells
12
, each cell
12
consisting of a single transistor
14
and a single capacitor
16
. A given cell
12
of the DRAM array
10
may be accessed by activating a particular bit line and word line. As the cells
12
of the DRAM array are arranged in a grid, only one cell
12
will be accessed for each combination of word line and bit line.
For example, in order to write a data bit into cell (
0
,
1
), word line
0
is activated by applying an appropriate voltage to that line, e.g., a logic high (such as 3.3V, 5V, 15V, etc.) or a logic low (such as 0V). The appropriate voltage on word line
0
will turn on each of the transistors
14
connected to that line including the transistor
14
of cell (
0
,
1
). A voltage may then be presented on bit line
1
, which will charge the capacitor
16
of cell (
0
,
1
) to a desired level, e.g., a logic high or logic low consistent with the data bit. The voltage may be presented on bit line
1
(and/or any of the other bit lines) by way of a suitably connected data bus. When the voltage on word line
0
is removed, the transistor
14
of cell (
0
,
1
) is biased off and the charge on the capacitor
16
of cell (
0
,
1
) is stored.
Reading a data bit from a particular cell
12
, such as cell (
0
,
1
), is substantially similar to writing a data bit except that the voltage on bit line
1
is imposed by the capacitor
16
of the cell
12
rather than by the data bus. Typically, a single cell
12
is not written to or read from; rather, an entire word (series of data bits) is written into the DRAM array
10
or read from the DRAM array
10
by applying the appropriate voltage on a particular word line and either imposing or sensing voltage on each of the bit lines
0
,
1
,
2
, etc.
Once data bits (i.e., voltages) have been stored on the capacitors
16
of the DRAM array
10
, the data are not permanent. Indeed, various leakage paths exist around the capacitors
16
and, therefore, failure to read the date may corrupt the stored voltages. In order to avoid the loss of data stored in the DRAM array
10
, the data are refreshed on a periodic basis. In particular, an external sense amplifier is employed to sense the data stored in the DRAM array
10
and rewrite (i.e., refresh) the data onto the capacitors
16
. Typically, the data associated with a particular word line (i.e., one data word) are refreshed every 7.8 microseconds (e.g., for 256 Mbit DRAM arrays) or every 15.6 microseconds (e.g., for 64 Mbit DRAM arrays). The refresh rate for a particular DRAM array
10
is established by the manufacturer and is based on a worst-case high temperature condition.
The refresh process may be implemented in either of two ways, namely, internally (self refresh) or externally (CBR or Ras only refresh). The internal refresh process requires that the DRAM itself set the refresh timing. The external refresh process requires an external chip (chipset) that issues a refresh command. The DRAM receives the refresh command from the external chip through a dedicated pin.
Unfortunately, the refresh process has a deleterious effect on overall system performance. Among these deleterious effects are: (i) an increase in power consumed by the DRAM array
10
and any external circuitry involved in the refresh process; and (ii) a decrease in overall system bandwidth. As to the former, the external sense amplifiers and other associated circuitry (e.g., row decoders, column decoders, etc.) involved in the refresh process, not to mention the DRAM array
10
itself, draw power in order to rewrite the data into the DRAM array
10
. In certain applications, such as in the automotive industry, power efficiency is desirable and increases in power consumption due to DRAM array
10
refresh cycles may be problematic. As to the latter, the refresh cycles of the DRAM array
10
take priority over routine reading and writing cycles and, therefore, the rate at which the DRAM array
10
is refreshed has a corresponding impact on the bandwidth (e.g., data throughput) of the overall system in which the DRAM array
10
is utilized.
Accordingly, there is a need in the art for a new device, system, and/or method for refreshing the data of a DRAM array such that power consumption is reduced and system bandwidth is increased.
SUMMARY OF THE INVENTION
In accordance with at least one aspect of the present invention, an apparatus includes: at least one DRAM array; and at least one temperature sensor in thermal communication with the DRAM array and operable to produce a signal indicative of a temperature of the DRAM array.
Preferably, the DRAM array is refreshed at a rate that varies in response to the signal. For example, the rate at which the DRAM array is refreshed may decrease as the temperature of the DRAM array decreases. Further, the rate at which the DRAM array is refreshed may increase as the temperature of the DRAM array increases.
Preferably, the at least one temperature sensor includes at least one diode having a forward voltage drop that varies as a function of the temperature of the DRAM array, and the signal corresponds to the forward voltage drop of the at least one diode. Alternatively, the at least one temperature sensor may be taken from the group consisting of thermocouples, thermistors, or any other device that provides an output signal that varies as a function of temperature.
In accordance with one or more further aspects of the invention, the apparatus may further include a refresh unit operable to refresh the DRAM array at a rate that varies in response to the signal. Preferably, the refresh unit includes a refresh timing unit operable to establish the rate at which the DRAM array is refreshed in response to the signal. It is preferred that the refresh timing unit is operable to decrease the rate at which the DRAM array is refreshed as the signal indicates that the temperature of the DRAM array decreases. It is also preferable that the refresh timing unit is operable to increase the rate at which the DRAM array is refreshed as the signal indicates that the temperature of the DRAM array increases.
When the at least one temperature sensor is a diode, it is preferable that the refresh unit is operable to sense the forward voltage drop of the diode to determine the temperature of the DRAM array.
In accordance with one or more further aspects of the present invention, the DRAM array and the at least one temperature sensor are disposed in a semiconductor package, the package including at least one connection pin operable to provide the signal to external circuitry.
In accordance with one or more further aspects of the invention, the DRAM array, the at least one temperature sensor, and the refresh unit are integrated in a semiconductor package.
In accordance with at least one further aspect of the present invention, the apparatus includes: at least one DRAM chip including the DRAM array and the at least one temperature sensor; at least one refresh chip operable to refresh the DRAM array at a rate that varies in response to the signal. Preferably, the refresh chip includes the refresh timing unit.
In accordance with one or more further aspects of the present invention, a method includes: sensing a temperature of a DRAM array; and refreshing contents of the DRAM array at a rate that varies in response to the temperature thereof.
The method preferably further includes decreasing the rate at which the DRAM array is refreshed as the tempera

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