Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-01
2002-06-04
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000
Reexamination Certificate
active
06399977
ABSTRACT:
FIELD OF THE INVENTION
The invention generally relates to device fabrication such as random access memories and, more particularly, to reducing oxidation stress at the shallow trench isolation interface.
BACKGROUND OF INVENTION
In device fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The layers are patterned to create features and spaces. The minimum dimension or feature size (F) of the features and spaces depend on the resolution capability of the lithographic systems. The features and spaces are patterned so as to form devices, such as transistors, capacitors, and resistors. These devices are then interconnected to achieve a desired electrical function. The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, and etching. Such techniques are described in S.M. Sze,
VLSI Technology,
2nd ed., New York, McGraw-Hill, 1988, which is herein incorporated by reference for all purposes.
Random access memories, such as dynamic random access memories (DRAMs), comprise memory cells that are configured in rows and columns to provide storage of information. One type of memory cells includes, for example, a transistor connected to a trench capacitor. Typically, the capacitor is referred to as the “node” when activated, the transistor allows information to be read or written into the capacitor.
Continued demand to device miniturization to have resulted in DRAMs with smaller feature size and cell area. For example, reduction of the conventional cell area of 8F
2
towards and below 6F
2
have been investigated. However, the fabrication of such small feature and cell sizes creates oxidation stress. The oxidation stress, in turn, creates dislocations which increases the node leakage current. Such increases in node leakage current adversely impacts the performance and operability of the memory cells.
From the above discussion, it is apparent that there is a need to reduce oxidation stress that results during the fabrication of devices.
SUMMARY OF INVENTION
The invention generally relates the reduction of oxidation stress at the shallow trench isolation interface. In one embodiment, a random access memory cell implemented with a trench capacitor is provided with a raised shallow trench isolation. The trench capacitor, which is formed below the top surface of a substrate, such as a silicon wafer, serves as the storage node of the memory cell. The top surface of the raised shallow trench isolation is raised above the top surface of the silicon substrate to reduce oxidation stress. The amount that the top surface of the shallow trench isolation is raised is sufficient to prevent the bottom of the divot formed during processing from being below the silicon surface.
REFERENCES:
patent: 6037620 (2000-03-01), Hoenigschmid et al.
patent: 6140175 (2000-10-01), Kleinhenz et al.
patent: 6140673 (2000-10-01), Kohyama
patent: 6153902 (2000-11-01), Furukawa et al.
patent: 6259129 (2001-07-01), Gambino et al.
patent: 5-347390 (1993-12-01), None
Meier Stephen D.
Siemens Aktiengesellschaft
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