Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-10-17
2002-11-05
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S666000
Reexamination Certificate
active
06475899
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit fabrication, and more particularly to a wiring layout which allows for a relatively high heat conductivity for a given capacitive-resistance load.
BACKGROUND
Multi-level wiring in integrated circuits is well known in the industry. In the early days of the semiconductor industry, nearly all of the resistance and the capacitive load in a circuit were in devices. As devices have grown smaller and the wiring cross-sections have been reduced, the capacitive load of the wiring structure and the line resistivity have grown to the point that they are the largest contributors to the total capacitive-resistance load on a device. Today, a major problem in the semiconductor processing industry is the capacitive-resistance effect in the wiring levels. Efforts to reduce the resistance of the wiring levels and to lower the capacitive loading on the wiring levels has met with poor results.
Conventionally, aluminum and aluminum alloys have been used for wiring integrated circuits. Aluminum, however, has a poor conductivity compared with other metals. Copper has also been used. However, copper, unlike aluminum, cannot be reactively ion etched. To be reactively ion etched, the object being etched must form a volatile compound at room temperature, and copper does not do so. Thus, wires, or lines, of copper must be formed in a damascene process. In the damascene process, a layer of insulating material is first deposited and patterned by reactive ion etching to form trenches. The conductor material, here copper, is deposited above a liner and adhesion layer within the trenches. Generally, the copper is deposited by either chemical vapor deposition (CVD) or electroplating. Any unwanted copper and liner may be removed by chemical mechanical polishing (CMP).
As lithographic dimensions decrease, the capacitive-resistance problem is increasing. The capacitive-resistance problem is effected by wires located in the same horizontal plane as well as by wires vertically separated. The capacitive effect of wires within the same plane is most directly affected by smaller lithographic dimensions. The horizontal and vertical capacitive effects can be mitigated to some extent by making the wiring thinner. Thinning the wiring, however, reduces the cross-section of the wiring, thereby increasing its resistance. Further, the vertical capacitive effect can be mitigated by increasing the thickness of the insulative material in which the various wiring layers are deposited. The insulative materials generally used have a low coefficient of thermal conductivity, thereby reducing the heat flow to the top surface of the integrated circuit, causing the integrated circuit to operate at a higher than desired temperature or a reduced power level to avoid an overheating problem.
Another solution to heat generation and dissipation is to make the wiring wider to increase the conductivity and/or electromigration resistance of the wiring. This, however, requires additional wiring planes, which consequently requires additional levels of insulative material, thereby reducing the ability to remove heat from the integrated circuit.
FIGS. 1-6
are exemplary depictions of conventional multiple level wiring layouts which have been used in integrated circuit designs.
FIGS. 1-6
show a portion of an integrated circuit have wiring channels running in a first direction at a first level interspersed with wiring channels at a second level running in a second direction perpendicular to the first direction. With specific reference to
FIGS. 1-2
, an integrated circuit portion
10
, which includes a substrate
13
, is shown having a top surface
12
, a bottom surface
14
, a first side surface
16
, a second side surface
18
, a third side surface
20
, and a fourth side surface
22
. A first plane of wiring
30
and a third plane of wiring
34
extend from the first side surface
16
to the third side surface
20
. A second plane of wiring
32
and a fourth plane of wiring
36
extend from the second side surface
18
to the fourth side surface
22
. Each of the wiring planes
30
,
32
,
34
,
36
include one or more wiring channels
38
into which are deposited conductive wires
40
. The wires may be formed of any conductive material, and are preferably formed of copper.
Each of the wiring planes
30
,
32
,
34
,
36
are set within and separated by an insulator material, such as an intralayer dielectric
42
. As shown, the second plane of wiring
32
is positioned between the first and third planes of wiring
30
,
34
, while the fourth plane of wiring
36
is beneath the third plane of wiring
34
. The width of each of the wiring channels
38
is generally equivalent to the height of the channels
38
, and the pitch is, for example, twice as long as either the height or the width of the channels
38
.
FIG. 3
illustrates another integrated circuit
100
having an alternative wiring layout configuration. The major difference between integrated circuit
100
and integrated circuit
10
is the configuration of the wiring channels, and hence the configuration of the wiring itself. Wiring channels
138
have a height twice that of the width of the channels
138
, and hence the wiring
140
has a greater height than width.
FIG. 4
illustrates another integrated circuit
200
having a plurality of channels
238
into which wiring
240
is deposited. Channels
238
have a height to width ratio of four to one.
FIG. 5
illustrates another integrated circuit
300
having an additional four planes of wiring beneath the four planes of wiring
30
,
32
,
34
,
36
. Specifically, beneath the fourth plane of wiring
36
is a fifth plane of wiring
331
which extends in a direction parallel to the first and third planes of wiring
30
,
34
, namely from the first side surface
16
to the third side surface
20
. Beneath the fifth plane of wiring
331
are a sixth plane
333
, a seventh plane
335
, and an eighth plane
337
. The seventh plane of wiring
335
extends from the first side surface
16
to the third side surface
20
, while the sixth and eighth planes of wiring
333
,
337
extend from the second side surface
18
to the fourth side surface
22
. As with the first four planes of wiring
30
,
32
,
34
,
36
, the second four planes of wiring
331
,
333
,
335
,
337
are interspersed such that each plane does not extend in the same direction as adjacent planes.
FIG. 6
illustrates another integrated circuit
400
which is similar to integrated circuit
300
(FIG.
5
). The difference is that each of the wiring channels
38
in a single plane of wiring is offset relative to the next closest wiring plane extending in the same direction. For example, the wiring channels
38
in the first wiring plane
30
are offset relative to the channels
38
in the third wiring plane
34
. Further, the channels
38
in a fifth wiring plane
431
are offset relative to the channels
38
in a seventh wiring plane
435
, and channels
38
in a sixth wiring plane
433
are offset relative to those in an eighth wiring plane
437
.
The wiring layouts illustrated in
FIGS. 1-6
all have capacitive-resistance effects. The capacitive-resistance effect (RC) of the integrated circuit
10
of
FIGS. 1-2
can be expressed by the equation
RC=
2
r
{acute over (&egr;&egr;)}
o
L
2
(4/
p
2
+1/
T
2
)
where r equals interconnect resistivity, {acute over (&egr;)}
o
equals permittivity of free space, {acute over (&egr;)} equals the dielectric constant of the insulator material, L is the interconnect length, p is the interconnect pitch, and T is the interconnect thickness. The interconnect resistivity r is a function of the material from which the wire is formed, and cannot be increased as the pitch and/or the thickness of the wire is reduced. It is also assumed that the thickness of the insulator material between the wiring planes is equal to the thickness of the wiring
40
, and the width of the wiring
40
is equal to one half the pitch.
Reduction and dissipation of heat caused by
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Quach T. N.
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