Semiconductor storage device

Details Semiconductor storage device Semiconductor storage device

1999-04-12

2002-08-27

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C257S350000, C257S351000

Reexamination Certificate

active

06441448

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a static semiconductor storage device (hereinafter referred to as SRAM) using field-shield isolation.
2. Description of Related Art
In general, an SRAM memory cell is constituted of six transistors.
FIG. 13
is an equivalent circuit diagram of an SRAM memory cell. In
FIG. 13
, reference symbols
1
a
and
1
b
denote access transistors each being an n-type transistor;
2
a
and
2
b
, driver transistors each being an n-type transistor;
3
a
and
3
b
, load transistors each being a p-type transistor;
4
a
and
4
b
, bit lines; and
5
, a word line. In the memory cell, the driver transistors
2
a
and
2
b
and the load transistors
3
a
and
3
b
form a flip-flop circuit.
FIGS. 14 and 15
show patterns of a related SRAM memory cell in which polysilicon interconnections in one level and metal interconnections in two levels and field-shield isolation plates are used on an SOI (silicon on insulator) substrate. Specifically,
FIG. 14
shows a pattern of field-shield isolation plates, active regions, polysilicon interconnections, first-level metal interconnections, and first contact portions that connect the first-level metal interconnections to the polysilicon interconnections or the active regions.
FIG. 15
shows a pattern of the field-shield isolation plates, the active regions, the polysilicon interconnections, second-level metal interconnections, and second contact portions that connect the second-level metal interconnections to the active regions or the field-shield isolation plates. The term “field-shield isolation” as used in this specification means, in simple terms, device isolation that utilizes off-states of MOS transistors having a high threshold voltage. The term “field-shield isolation plate” corresponds to the gate of an ordinary transistor. In the following description, the field-shield isolation will be explained in a case where it is effected by field-shield isolation plates.
To reduce the resistivity of active regions on an SOI substrate, usually the surface portions of the active regions are converted to a refractory metal silicide.
In the related SRAM memory cell pattern of
FIG. 14
,
11
a
-
11
c
denote field-shield isolation plates for n-type transistors;
11
d
, a field-shield isolation plate for p-type transistors;
12
a
-
12
f
, n-type active regions;
12
g
-
12
j
, p-type active regions;
12
x
-
12
z
, active regions that are not clearly judged to be of an n-type or of a p-type; and
13
a
-
13
c
, polysilicon interconnections or interconnections having a laminated structure of polysilicon and a silicide (hereinafter represented by polysilicon interconnections). Reference symbols
14
a
-
14
c
denote first-level metal interconnections, and
15
a
-
15
h
denote first contact portions that connect the first-level metal interconnections to the active regions or the polysilicon interconnections.
In
FIG. 15
, reference symbols
16
a
-
16
d
denote second-level metal interconnections, and
17
a
-
17
f
denote second contact portions that connect the second-level metal interconnections to the active regions or the field-shield isolation plates.
Next, the components shown in the equivalent circuit diagram of
FIG. 13
will be correlated with the parts shown in
FIGS. 14 and 15
. As for the access transistors, for the sake of convenience, the active regions connected to the bit lines will be called drain active regions and the active regions connected to the driver transistors will be called source active regions. First, as for the transistors, the drain active region, the gate, and the source active region of the access transistor
1
a
are the parts
12
a
,
13
a
, and
12
b
, respectively; those of the access transistor
1
b
are the parts
12
d
,
13
a
, and
12
e
, respectively; those of the driver transistor
2
a
are the parts
12
b
,
13
b
, and
12
c
, respectively; those of the driver transistor
2
b
are the parts
12
e
,
13
c
, and
12
f
; those of the load transistor
3
a
are the parts
12
g
,
13
b
, and
12
h
; and those of the load transistor
3
b
are the parts
12
i
,
13
c
, and
12
j
. The bit line
4
a
corresponds to the part
16
a
, the bit line
4
b
corresponds to the part
16
b
, and the word line
5
corresponds to the part
13
a
. The part
14
c
in
FIG. 14
corresponds to the Vcc interconnection and the parts
16
c
and
16
d
in
FIG. 15
correspond to the GND interconnection.
FIG. 16
is a sectional view taken along line I—I in
FIGS. 14 and 15
. In
FIG. 16
, reference symbols
21
-
23
denote a silicon portion, an insulating layer, and an interlayer insulating film, respectively.
The above-described SRAM formed on the SOI substrate by using the field-shield isolation have the following three problems.
The first problem is data destruction at storage nodes that occurs being influenced by floating potential regions. In
FIG. 14
, although the active regions
12
x
-
12
z
are divided from each other by the field-shield isolation plates
11
b
and
11
d
and the polysilicon interconnections
13
b
and
13
c
, their potentials are not fixed. Therefore, the active regions
12
x
-
12
z
are rendered in a floating potential state and influence the active regions
12
b
,
12
e
,
12
g
, and
12
i
as storage node portions in memory cell operation, and possibly cause data destruction through noise, latch-up, or the like.
The second problem is a large memory cell size. As shown in
FIG. 14
, the potentials of the field-shield isolation plate
11
b
for n-type transistors and the field-shield isolation plate
11
d
for p-type transistors are fixed at the GND potential and the Vcc potential, respectively. Therefore, intervals are needed between the n-type transistors and the p-type transistors. Specifically, if each of a minimum field-shield isolation width (or a minimum polysilicon interconnection width) and a minimum isolation interval (or a minimum polysilicon interval) is W, it is desirable that an interval X between the same storage nodes (see
FIG. 14
) be equal to 3W. However, actually, since the active regions
12
x
-
12
z
between the n-type transistors and the p-type transistors are electrically unstable (the first problem mentioned above), there may occur latch-up or the like. For this reason, to make the memory cell less prone to data destruction, the interval X between the same storage nodes is set at a large value 3W+&agr;. This necessarily increases the memory cell size.
The third problem is severe hole forming conditions of the second contact portions.
FIG. 17
shows a pattern of field-shield isolation plates in a case where related memory cells
40
as shown in
FIGS. 14 and 15
are arranged in a 4×4 (vertical/horizontal) array. Where the field-shield isolation plates
11
b
and
11
d
are arranged in array form, they assume a continuous pattern and hence the plate potentials can be fixed at ends of the array.
On the other hand, where the field-shield isolation plates
11
a
and
11
c
are solitary patterns, the plate potentials need to be fixed at the respective positions. As shown in
FIG. 15
, it is necessary to fix the potentials by connecting the field-shield isolation plates
11
a
and
11
c
to the second-level metal interconnections
16
d
and
16
c
via the second contact portions
17
d
and
17
c
, respectively.
Therefore, as shown in
FIG. 15
, it is necessary to form, in the memory cell, two kinds of second contact portions having different depths, that is, the contact portions
17
a
,
17
b
,
17
e
, and
17
f
for the active regions and the contact portions
17
c
and
17
d
for field-shield isolation plates, which leads to severe contact hole opening conditions.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problems in the art, and a first object of the invention is therefore to eliminate floating potential active regions.
A second object of the invention is to reduce the memory cell size.
A third object of the invention is to realize a memory cell configuration in which s

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