Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-07-12
2002-06-25
Mai, Son (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S205000, C365S222000
Reexamination Certificate
active
06411541
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a method for controlling a re-writing operation for a memory cell in a semiconductor integrated circuit that is equipped with a memory cell including a capacitor as a charge storing capacitor and a switching element as a transfer gate, a semiconductor integrated circuit, a semiconductor device equipped with many of the semiconductor integrated circuits, and an electronic apparatus using the semiconductor device, and more particularly to a technology to control a plate line when a re-writing operation is conducted after a reading operation of the memory cell is conducted.
2. Conventional Technology
A conventional semiconductor integrated circuit structure equipped with capacitors having ferroelectric films and their operation are shown in a block diagram in FIG.
5
and in a timing chart shown in
FIG. 6
, respectively.
First, the circuit structure shown in
FIG. 5
is described. As being well known, memory cells
1
and
2
arranged side by side include, as their components, capacitors
5
and
7
as charge storage capacitors formed from ferroelectric films, and Nch transistors
4
and
6
as transfer gates for switching the capacitors, respectively. Each of the memory cells
1
and
2
is connected through a bit line BL to a sense amplifier
3
for reading data.
Gates of the Nch transistors
4
and
6
of the memory cells are connected to corresponding independent word lines WL
1
and WL
2
, respectively. The bit line BL is connected to one of the source/drain of each of Nch transistors
8
and
14
, respectively. The other of the source/drain of each of the Nch transistors
8
and
14
is grounded, and gates thereof are connected to signal lines for providing a pre-charge signal PRC.
The sense amplifier
3
is formed from Pch transistors
9
and
10
, and Nch transistors
11
~
13
. One of so urce/drain of the Pch transistor
9
and one of source/drain of the Pch transistor
10
are connected to one another, and a gate of the Pch transistor
9
and the other of source/drain of the Pch transistor
10
are both connected to the bit line BL. A reference potential VREF from a reference potential generation circuit (not shown) is inputted in a gate of the Pch transistor
10
, the other of source /drain of the Pch transistor
9
, and one of source/drain of each of the Nch transistor
11
and
12
. The other of source/drain of each of the Nch transistors
11
and
12
is connected to one of source/drain of the Nch transistor
13
. The other of source/drain of the Nch transistor
13
is grounded, and its gate receives an input of a sense amplifier drive signal SA.
As described above, the bit line BL that passes the sense amplifier circuit
3
(node A) is connected to one of source/drain of the Nch transistor
14
, and is also connected to an input terminal of an inverter circuit
15
. An output terminal of the inverter circuit
15
is connected to input terminals of inverter circuits
16
and
17
, and an output terminal of the inverter circuit
16
is connected to the input terminal of the inverter circuit
15
. Information read from the memory cells
1
and
2
by the sense amplifier circuit
3
are outputted as data (“Data output” in the figure) from an output terminal of the inverter circuit
17
.
It is noted that the block selection circuit (not shown) outputs a block signal to thereby select among the signal lines (WL
1
, WL
2
, PL) that are subject to being driven to select either the memory cell
1
or
2
that is subject to a reading operation or a writing operation.
Next, a writing operation is described. When writing in the memory cell
1
, the pre-charge signal PRC is lowered from the power supply potential VDD to the GND potential, then the potential on the bit line BL is set to the GND potential, and the GND potential on the word line WL
1
is set to the power supply potential VDD to thereby put the transistor
4
in an ON state. When input data is H data, a wiring circuit (not shown) sets the potential on the bit line BL to the power supply potential VDD, and the potential on the plate line PL to the GND potential, such that an electric field directed from the bit line to the plate line is applied to the ferroelectric capacitor
5
. As a result, a charge (data) associated with a polarization corresponding to the strength of the electric field and its direction can be written in the ferroelectric capacitor
5
. When the input data is L data, the potential on the bit line BL is set to the GND potential, and the potential on the plate line PL is set to the power supply potential VDD, such that an electric field directed from the plate line to the bit line is applied to the ferroelectric capacitor
5
. As a result, a charge (data) associated with a polarization corresponding to the strength of the electric field and its direction can be written in the ferroelectric capacitor
5
. Subsequently, the power supply potential VDD on the word line WL
1
is set to the GND potential to put the transistor
4
in an OFF state to thereby retain the written data, and complete the writing operation.
On the other hand, for the memory cell
2
, the word line WL
2
is retained at the GND potential to put the transistor
6
in an OFF state and a writing operation is not conducted.
Next, a reading operation is described with reference to FIG.
5
and FIG.
6
.
FIG. 6
is a timing chart of a reading operation. When the memory cell
1
is read, the pre-charge signal PRC is lowered from the power supply potential VDD to the GND potential, and the potential on the bit line BL is set to the OND potential, and then the GND potential on the word line WL
1
is set to the power supply potential VDD to put the transistor
5
in an ON state. Next, the potential on the plate line PL is changed from the GND potential to the power supply potential VDD, with the result that a potential corresponding to a charge (data) associated with a polarization retained in the ferroelectric capacitor
4
is generated on the bit line BL. Here, the reference potential VREF of the sense amplifier
3
is set at a value intermediate of the bit line potentials that are to be generated respectively corresponding to H level and L level of data. When the sense amplifier drive signal SA is elevated from the GND potential to the power supply potential VDD, the sense amplifier
3
immediately detects and amplifies the magnitude of the potential, such that data corresponding to H level or L level of memory cell data is outputted. In other words, when the data is at H level, the bit line potential is greater than the reference potential VREF, such that the potential VA at the node A is at H level and H data is outputted. When the data is at L level, the bit line potential is smaller than the reference potential VREF, such that the potential VA at the node A remains to be at L level, and L data is outputted (this is referred to as a sense operation).
Here, when the data is H data, in association with the reading operation, an electric field directed from the plate line to the bit line is once applied to the ferroelectric capacitor
4
. As a result, the data is destroyed (becomes L data). Therefore, while the sense amplifier drive signal SA is retained at the power supply potential VDD, and the potential on the bit line BL (that is equal to the potential VA at the node A in the figure) is retained at the power supply potential VDD, it needs to wait until time t
2
to shift the potential on the plate line PL from the power supply potential VDD to the GND potential to apply to the capacitor
5
an electric field directed from the bit line to the plate line to thereby re-write data H. The reading operation is completed after the re-writing operation is completed.
In the conventional technology, to suppress variations in the bit line potential due to variations in the memory cells, the timing at which the potential on the plate line PL is shifted from the power supply potential VDD to the GND potential has to be delayed until time t
2
show
Harness & Dickey & Pierce P.L.C.
Mai Son
Seiko Epson Corporation
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