Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-13
2002-08-06
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S369000
Reexamination Certificate
active
06429485
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating a thin film transistor (TFT) which enables heavily doped regions and lightly doped regions to form simultaneously by a single doping process by differentiating the thickness of a gate insulating layer.
2. Discussion of Related Art
A current driving efficiency of a polycrystalline TFT is higher than that of an amorphous silicon TFT during its on-state, while a leakage current of the polycrystalline TFT is higher than that of the amorphous silicon TFT during its off-state. When switching devices in a pixel array are comprised of polycrystalline TFTs, image display performance of a liquid crystal display (LCD) is decreased by a signal value stored in a pixel electrode wherein the signal value varies due to a relatively large leakage current during the off-state. That is why techniques of forming switches which have structures of LDD (lightly doped region) or offset have been proposed for poly silicon TFTs.
FIGS. 1A
to
1
D show a method of fabricating an LDD TFT according to a related art. Referring to
FIG. 1A
, an active layer
11
is defined by patterning a polycrystalline silicon layer which has been formed on an insulated substrate
10
. The polycrystalline silicon layer may be formed by depositing amorphous silicon on the insulated substrate
10
and then by crystallizing the amorphous silicon with dehydrogenation and a laser annealing process. After that, a first insulating layer
13
L and a first conductive layer
15
L are formed in order on the disclosed surfaces of the active layer
11
and the insulated substrate
10
. Then, a photoresist pattern (PR) for forming a gate is defined by a photoresist coating, selective exposure and development.
Referring to
FIG. 1B
, a gate electrode
15
is formed by etching the first conductive layer
15
L by using the photoresist pattern (PR) as an etching mask. After the photoresist pattern has been removed, a gate insulating layer
13
is defined by patterning the first insulating layer
13
L by using the gate electrode
15
as an etching mask.
Referring to
FIG. 1C
, a doping-blocking layer B is formed to cover the gate region including the gate electrode
13
and the gate insulating layer
15
and also to cover its peripheral region. The doping-blocking layer B may be formed by using a photoresist. Each of ‘LL’ and ‘LR’, which represents LDD regions, in the drawing depicts a length which is covered by the doping-blocking layer B but not overlapped with the gate electrode
15
. The doping-blocking layer B defines the boundaries of LDD regions in the active layer
11
. Thereafter, a source region
11
S and a drain region
11
D are formed by doping heavily the exposed parts of the active layer
11
with n typed impurities.
Referring to
FIG. 1D
, the LDD region
11
L in the active layer
11
is lightly doped with the n typed impurities by a lightly doping process after the doping-blocking layer B has been removed. In this case, having been doped heavily with the n typed impurities, the source region
11
S and the drain region
11
D are not affected by the density of impurities during the lightly doping process. Then, the regions having been doped with the impurities are activated by a thermal treatment or a laser annealing of the substrate.
In order to form the LDD region, the related art has a problem of adding a series of complicated steps, such as a doping-blocking layer, lightly doping with impurities, activating the impurities and the like, thereby requiring multiple processes.
Moreover, as the LDD region is defined by the doping-blocking layer, the LDD region is difficult to be patterned symmetrically when the channel is taken as a given center. In other words, each length of the left and the right LDD region represented respectively by ‘LL’ and ‘LR’ shown in
FIG. 1C
is not identical to each other. That results from such factors as a bent substrate, a mis-alignment of the doping-blocking layer, etc.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of fabricating a thin film transistor that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
The object of the present invention is to provide a method of fabricating a thin film transistor which enables heavily doped regions and lightly doped regions to form simultaneously by a single doping process by differentiating the thickness of a gate insulating layer. The present invention uses impurity distribution to a depth direction in accordance with a range of projection.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes the steps of forming an active layer on an insulated substrate, forming a first insulating layer on the active layer, forming a first conductive layer on the first insulating layer, forming a first photoresist pattern on the first conductive layer, forming a gate electrode within a scope of the first photoresist pattern by over-etching the first conductive layer by using the first photoresist pattern as an etch mask, partially etching the first insulating layer by using the first photoresist pattern as an etch mask, wherein a part of the first insulating layer which is overlapped with the first photoresist pattern is thicker, removing the first photoresist pattern, and doping heavily a surface of the substrate with impurities.
In another aspect of the present invention, the present invention having a first typed transistor and a second typed transistor includes the steps of forming active layers for the first typed transistor and the second typed transistor on an insulated substrate, forming a first insulating layer on the active layers, forming a first conductive layer on the first insulating layer, forming first photoresist patterns on the first conductive layer wherein each of the first photoresist patterns is overlapped with predetermined portions of the active layers, forming gate electrodes for the first typed and the second typed thin film transistors within each scope of the first photoresist patterns by over-etching the first conductive layer by using the first photoresist patterns as etch masks, under-etching the first insulating layer of the first photoresist patterns as etch masks wherein parts of the first insulating layer which are overlapped with the first photoresist patterns is thicker than is not, removing the first photoresist patterns, forming a heavily-doped first typed impurity region and a lightly-doped first typed impurity region in the active region of the first typed thin film transistor by doping the first typed thin film transistor with first typed impurities, and forming a heavily-doped second typed impurity region and a lightly-doped second typed impurity region in the active region of the second typed thin film transistor by doping the second typed thin film transistor with second typed impurities.
In a further aspect of the present invention, the present invention having a first typed transistor and a second typed transistor includes the steps of forming each active layer of the first typed and the second typed TFT on an insulated substrate, forming a first insulating layer covering the active layers, forming a first conductive layer on the first insulating layer, forming first photoresist patterns on the first conductive layer wherein each of the first photoresist pattern is overlapped with predetermined portions of each of the active layers, forming a first and a second gate of the first and said second typed thin film transi
Ha Yong-Min
Park Jae-Deok
LG. Philips LCD Co. Ltd.
McKenna Long & Aldridge LLP
Prenty Mark V.
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