Method and system for controlling the memory access...

Details Method and system for controlling the memory access... Method and system for controlling the memory access...

1999-06-18

2002-10-22

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S167000

Reexamination Certificate

active

06470416

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88103132, filed Mar. 2, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a computer memory access technique, and more particularly, to a method and system for use on a computer system to control a memory access operation by a central processing unit (CPU) of a memory unit in a more efficient manner by means of transferring each read request promptly to the memory unit without waiting until the L
1
write-back signal for the read request is issued, and also by means of utilizing the auto-precharge feature of the memory unit.
2. Description of Related Art
In this information age, computers have become an indispensable data processing tool in all walks of life. In the use of computers, performance is a primary concern. Many factors can affect the performance of a computer system, including the speed of the CPU, the type of the primary memory being used, efficiency of memory access control, and so forth. Presently, dynamic random-access memory (DRAM) is widely used as the primary memory of most computer systems. Conventional memory access methods that can help boost computer performance include, for example, the Fast Page Mode (FPM) method and the Extended Data Out (EDO) method. Moreover, a new type of DRAM, called synchronized DRAM (SDRAM), allows high-speed access to the data stored therein.
FIG. 1
is a schematic block diagram of the system configuration of a conventional memory access control method and system, as indicated by the reference numeral
120
, which is designed to control the memory access operation by a CPU
110
of a memory unit
130
.
The memory access control system
120
is coupled between the CPU
110
and the memory unit
130
and is composed of a CPU interface
121
and a memory control unit
122
. The CPU
110
further includes a cache memory
112
. The CPU
110
and the CPU interface
121
are interconnected via a number of data lines ADS, REQ, HITM, HA, HD, DBSY, and DRDY; the CPU interface
121
and the memory control unit
122
are interconnected via two data lines DADS and DAT; and the memory control unit
122
and the memory unit
130
are interconnected via three data lines CMD, MD, and CS
0
.
The access operation by the CPU
110
of the memory unit
130
, whether read or write, is controlled by the memory access control system
120
. The data communication between the CPU
110
and the memory control unit
122
is controlled by the CPU interface
121
. When the CPU
110
wants to gain access to the memory unit
130
, it issues access requests via the CPU interface
121
to the memory control unit
122
. In the case of a write operation, the memory control unit
122
is used to control the writing of the output data from the CPU
110
into the memory unit
130
. In the case of a read operation, the memory control unit
122
controls the retrieval of the CPU-requested data from the memory unit
130
and then transfers the retrieved data via the CPU interface
121
to the CPU
110
.
When the CPU
110
wants to gain access to the memory unit
130
, it first sets the ADS data line at a LOW-voltage logic state. Whether the intended access operation is write or read is indicated by the logic voltage state of the REQ data line. Moreover, whether the request is a hit or a miss to the cache memory
112
is indicated by the logic voltage state of the HITM data line. For instance, in the case of a cache hit, the HITM data line is set at a LOW-voltage logic state, whereas in the case of a cache miss, the HITM data line is set at a HIGH-voltage logic state (the signal on the HITM data line is hereinafter referred to an L
1
write-back signal). When the DRDY and DBSY data lines are set at A LOW-voltage logic state, this indicates that the CPU interface
121
wants to transfer data via the HD data line to the CPU
110
. Moreover, the HA data line is used to transfer address signals from the CPU
110
.
Furthermore, the CPU interface
121
and the memory control unit
122
use the DADS and DAT data lines for internal data communication therebetween. The DADS signal is a converted version of the ADS signal from the CPU
110
. The DAT data line is used to transfer the output data from the CPU
110
that are to be written into the memory unit
130
, or the data that are retrieved from the memory unit
130
and to be transferred via the CPU interface
121
to the CPU
110
.
The memory control unit
122
and the memory unit
130
use the CMD, MD, and CS
0
data lines for data communication therebetween. The CMD data line is used to transfer access control signals issued by the memory control unit
122
to the memory unit
130
; the MD data line is used to transfer memory data to and from the memory unit
130
; and the CS
0
data line is used to transfer a chip-select signal to the memory unit
130
. The chip-select signal is enabled when the CS
0
data line is set at a LOW-voltage logic state.
The storage space of the memory unit
130
is partitioned into a plurality of pages
135
. To read data from the memory unit
130
, the CPU
110
issues a number of read requests successively to the CPU interface
121
. If any one of the read requests is a hit to the cache memory
112
, the CPU
110
uses the HITM data line to issue an L
1
write-back signal to indicate such a condition to the memory control unit
122
, and in which case, a cache write-back operation is performed to write the cache data back into the memory unit
130
. Typically, the L
1
write-back signal of each read request is issued several clock cycles after the read request is issued. The conventional memory access control system
120
operates in such a manner that, for each read request from the CPU
110
, the CPU interface
121
waits until the L
1
write-back signal of the current read request is received and then send out the corresponding internal read-request signal to the memory control unit
122
. In response to this internal read-request signal, the memory control unit
122
then performs a read operation to retrieve the requested data from the memory unit
130
and then transfers the retrieved data via the CPU interface
121
to the CPU
110
.
Presently, SDRAM is widely used to implement the memory unit
130
. The SDRAM comes with many advanced features, such as the auto-precharge feature which allows the SDRAM to undergo an auto-precharging operation after the completion of a read operation. The auto-precharge feature can help reduce the time required for precharging the SDRAM. However, this feature is not utilized by the conventional memory access control system
120
shown in
FIG. 1
to help enhance its memory access performance.
As a conclusion, there are two drawbacks to the prior art. First, there exists a waiting period for the CPU interface
121
to issue the internal read-request signal to the memory control unit
122
until the CPU
110
issues the L
1
write-back signal of the current read request; and second, the advanced auto-precharge feature of SDRAM is not fully utilized to help enhance memory access performance. The overall system performance of a computer system using the prior art is therefore poor and there is still room for improvement. Typically, the overall memory access operation performed by a CPU includes 60% read operation, 15% cache write-back, and 25% write operation. Therefore, the overall system performance of a computer system can be enhanced solely by increasing the speed of the read operation. The conventional method and system of
FIG. 1
, however, is low in read operation since it frequently must wait for L
1
write-back signals and requires a long period to precharge the memory unit.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide an improved memory access control method and system for use on a computer system, which can help increase the speed of the read operation by the CPU by means of transferring e

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