Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into...
Reexamination Certificate
2000-05-05
2002-02-12
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
C438S514000
Reexamination Certificate
active
06346463
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method for forming a semiconductor device with a tailored well profile.
2. Description of the Related Art
The manufacture of semiconductor devices frequently calls for doping a semiconductor substrate. The semiconductor substrate, or simply the “substrate,” is an underlying layer of material upon which a device or circuit is fabricated. To effect the electrical properties of the substrate various ions (e.g., dopants) are intentionally added to the silicon substrate to make it semi-conductive. Generally there are two types of dopants, positive-type (i.e., p-type) and negative-type (i.e., n-type). In current semiconductor device applications, the substrate includes a base layer of highly doped p-type silicon, covered by a layer of lightly doped p-type silicon, commonly formed above the substrate using an epitaxial growth process. This upper layer is commonly referred to as the EPI layer. Semiconductor manufacturers typically buy wafers with preformed EPI layers in bulk quantities and perform subsequent processing steps to form semiconductor devices on the wafer. The combination of the base silicon layer and the EPI layer are collectively referred to as the substrate.
To implement conducting features in the resultant device, portions of the EPI layer are doped with n-type or p-type dopants to create either n-type or p-type semiconductive pockets (e.g., commonly referred to as wells) in the substrate. Commonly, a semiconductor device includes both n-wells and p-wells. Individual devices, such as transistors, are formed in the various wells to construct the semiconductor device.
One early approach to introducing dopants into the EPI layer to form the wells involved the use of a process known as “thermal diffusion.” In thermal diffusion, the substrate is generally covered by a mask having holes that expose selected portions of the substrate. The wafer, i.e., the substrate and mask, are then heated to approximately 1000° C. in the presence of a vapor of the dopant material. The dopant then diffuses into the substrate through the holes in the mask to create the n-wells or p-wells. A more thorough treatment of the general principles of thermal diffusion may be found in Peter van Zant, Microchip Fabrication, pp. 312-330 (3d Ed. McGraw-Hill New York 1997) (ISBN 0-07-067250-4).
As the technology matured, the sizes of the features being constructed decreased dramatically. Eventually, thermal diffusion processes reached problematical technological limitations. One such limitation is “lateral diffusion,” which is the phenomenon by which the dopant diffuses not only down into the substrate, but also laterally beyond the openings in the mask. This means the designer must leave extra space between openings to account for the lateral diffusion. As feature sizes decrease, the negative contribution of this limitation increases. Other problems include ultra-thin junctions, poor doping control, surface contamination interference, and dislocation generation.
The industry consequently turned to a physical process called “ion implantation.” In ion implantation, atoms of the dopant material are ionized, accelerated to a high speed, and “shot” into the wafer surface. One analogy to this process is the a cannon ball shot into a wall. If shot with the right amount of force at a wall, the cannon ball will penetrate the wall and come to rest in the wall but below its surface. See van Zant, supra, p. 332. In a typical ion implantation process, the substrate is covered with a mask having openings formed therein and bombarded with dopant ions at high energy through the openings in the mask. The dopant ions thus create the n-wells and/or p-wells in the substrate. Additional information on general ion implantation principles may be found in van Zant, supra, pp. 332-347.
More technically, ion implantation is a semiconductor doping process whereby a plurality of dopant atoms are first ionized, accelerated to velocities sufficient to penetrate the semiconductor surface, and implanted therein. Dopants generally come in either p-type or n-type. P-type dopants (including boron, aluminum, gallium, thallium, indium and/or silicon) produce what is commonly known as hole conductivity, while n-type dopants (including phosphorous, arsenic, and/or antimony) produce what is commonly known as electron conductivity. Combinations of hole and electron-rich regions produce the desired devices such as transistors, resistors, diodes, capacitors, etc., that form the basis of semiconductor device operation. Recent advances in semiconductor manufacture include fine-line geometries of dopant materials on a substrate to form very large scale integrated devices.
Ion implantation resolves many of the problems from which thermal diffusion suffers and provides additional benefits. Among the benefits of ion implantation are: the process takes place at close to room temperature; the dopant is placed below the substrate surface; the concentration and location of the dopants can be more accurately controlled; a wider range of doping concentrations may be achieved; and greater flexibility in masking materials may be exercised. The greater control and relative lack of lateral diffusion make ion implantation especially useful in manufacturing devices with high density and small feature sizes. Because of these many benefits, ion implantation has largely displaced thermal diffusion, although thermal diffusion still finds some use.
Ion implantation, however, is not without its own limitations. The equipment is complex and expensive. The process employs higher voltages and more toxic gases than does thermal diffusion. A well is typically made using a series of implants (e.g., between 4 and 6) to provide dopant ions at different depths in the substrate. A subsequent annealing process is used to homogenize the various independent dopant layers and to repair damage to the lattice structures of the target material caused by the implantation process. One of the more important problems with ion implantation arises from the high energies used to create wells of adequate depth. The mask layer used to protect areas of the substrate where well formation is not desired must accommodate the deepest (i.e., highest energy) implant.
A cross section view of a partially completed semiconductor device
10
is shown in FIG.
1
. The semiconductor device
10
includes a base layer
20
on which an epitaxial silicon (EPI) layer
30
has been formed. A photoresist layer
40
has been formed and patterned to expose portion of the EPI layer
30
where well formation is desirable. Wells
50
are formed by implanting dopant ions into the exposed portions of the EPI layer
30
. The thickness of the photoresist layer
40
is dictated by the energy of the highest energy well implant. Such high energy implants necessitate relatively thick masks that, when used to fabricate small features, create a very large “aspect ratio.”
The portion
60
of the photoresist layer
30
disposed between the wells
50
exhibits such a high aspect ratio. Large aspect ratios reduce the achievable resolution with which the various features, such as the wells
50
, may be created. When the photoresist layer
40
is being patterned, it is typically developed in a wet environment. When a large aspect ratio mask feature
60
is formed between closely spaced wells
40
, the photoresist my fail to adhere to the substrate or may tip over during the developing process, thus compromising its functionality.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a method for forming a semiconductor device. A base layer is provided. A first epitaxial layer having a first dopant at a first concentration is formed above the base layer. A second epitaxial layer having a second dopant at a second concentration is formed above t
Hause Frederick N.
Sultan Akif
Elms Richard
Smith Brad
Williams Morgan & Amerson P.C.
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