Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-03
2002-12-10
Chaudhuri, Okik (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S550000
Reexamination Certificate
active
06492679
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to high voltage MOSFET semiconductor devices and more specifically to a method for manufacturing a high voltage MOSFET semiconductor device with reduced on-resistance.
When designing high voltage metal oxide semiconductor (MOS) devices two criteria must be kept in mind. First, the semiconductor device should have a high breakdown voltage (V
BD
). Second, the semiconductor device, when operating, should have a low on-resistance (RDS
ON
). One problem is that techniques and structures that tend to maximize breakdown voltage tend to adversely affect on-resistance and vice versa.
Different designs have been proposed to create semiconductor devices with acceptable combinations of breakdown voltage and on-resistance. One such family of semiconductor devices is fabricated according to the reduced surface field (RESURF) principle. Semiconductor devices with RESURF typically utilize an extended drain region, such as an nwell, to support high off-state voltage, i.e. an increase in breakdown voltage, V
BD
. Such RESURF semiconductor devices can have a charge in the drain area of about 1×10
12
atoms/cm
2
before avalanche breakdown occurs. The high charge sets up a low onresistance since on-resistance is inversely proportional to the charge in the extended drain region.
In order to reduce the on-resistance, some RESURF devices incorporate a top layer of a conductivity type opposite the extended drain region, such as a p-top layer, inside the extended drain region. The addition of the p-top layer into the extended drain region permits the charge in the extended drain to increase as compared to designs without a p-top layer, which in turn decreases the on-resistance significantly. Furthermore, when the extended drain region is supporting high voltage, the p-top layer aids in the depletion of the more heavily doped extended drain region, thus allowing for high breakdown voltage.
One drawback to this approach is that a high charge under the gate region and adjacent to the channel region can lead to premature breakdown when the device is blocking voltage.
REFERENCES:
patent: 6365457 (2002-04-01), Choi
patent: 6365941 (2002-04-01), Rhee
patent: 6369424 (2002-04-01), Nakamura et al.
patent: 2002/0017684 (2002-02-01), Blanchard et al.
patent: 2002/0024056 (2002-02-01), Miyakoshi et al.
Enosawa Yoshio
Fulton Joe
Hossain Zia
Imam Mohamed
Stefanov Evgueniy N.
Chaudhuri Okik
Semiconductor Components Industries LLC
Vesperman William C
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