Semiconductor device

Details Semiconductor device Semiconductor device

2000-04-11

2002-11-19

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S380000, C438S238000, C438S239000

Reexamination Certificate

active

06483152

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to an analog semiconductor device and a method of fabricating the same.
In general, an analog semiconductor device stores information of various states and is formed at the desired nodes of circuits. The analog semiconductor device includes a resistor and a capacitor and is for example, used for a timer in dynamic random access memory(“DRAM”). Herein, the timer makes the DRAM to automatically refresh without separate instructions from the external. The timer generates a pulse signal for refresh with a long period of 1-100 &mgr;s within a chip. The period of the timer for refresh depends on the values of a resistor and a capacitor and is proportion to product of resistance and capacitance. At this time, a resistor is formed as a polysilicon layer and a capacitor includes lower and upper plates and a dielectric film between the plates. The resistance of the resistor depends on an impurity concentration doped in the polysilicon layer and is previously determined in depositing the polysilicon layer. The capacitance of the capacitor is proportion to squares lower and upper plates and dielectricity of the dielectric film.
Such analog semiconductor device is simultaneously formed with devices such as DRAMs including a MOS transistor and a storage capacitor. Herein, in order to obtain fast switching speed of a MOS transistor in DRAM, the MOS transistor is formed as n-type. In order to improve conductivity, a self aligned silicide layer is formed over the gate electrode and junction regions in the MOS transistor.
However, the silicide layer is formed over the gate electrode and junction regions as well as over the resistor and the capacitor plate. At this time, the resistance of the resistor which is previously determined in formation, is varied by the overlying silicide layer, thereby causing the problem such that the DRAMs does not store the desired values.
FIGS. 1A through 1D
are sectional views illustrating a process of fabricating a conventional analog semiconductor device. Referring to
FIG. 1A
, a field oxide
2
is formed over a semiconductor substrate
1
by LOCOS to define the device region AA. A gate oxide
3
and a polysilicon layer are formed over the substrate
1
, in turn and then etched to form a resistor
41
, a gate electrode
42
of a MOS transistor and a lower plate of an analog capacitor. At this time, the resistor
41
and the lower plate
43
of an analog capacitor are formed at the predetermined portion of the semiconductor substrate, for example over the field oxide
2
and the gate electrode
42
of a MOS transistor is formed on the substrate
1
of the device region AA.
Next, impurity ions of a predetermined conductivity type opposite to the semiconductor substrate
1
are implanted into the substrate
1
at the both sides of the gate
42
, to form junction regions
5
, thereby forming a MOS transistor. Then, a first insulation layer is formed over the substrate
1
and then anisotropically etched to form first sidewall spacers
6
of both sides of the resistor
41
, the gate electrode
42
, and the lower plate
43
. Herein, the first spacers
6
are formed in order to be used in forming junction regions of a LDD structure and in forming a self-aligned silicide layer.
Afterwards, a dielectric layer
7
and a polysilicon layer
8
for an upper plate of an analog capacitor are formed respectively over the substrate
1
, and a first photoresist pattern
9
for an upper plate of a capacitor is formed over the lower plate
43
by a photolithography. Herein, the width of the photoresist pattern
9
is smaller than the width of the lower plate
43
.
Referring to
FIG. 1B
, the polysilicon layer
8
and the dielectric layer
7
are etched by using the photoresist pattern
9
as a mask, thereby forming an analog capacitor
10
including the lower and upper plates
43
and
8
and the dielectric layer
7
. Then, the photoresist pattern
9
is removed and a second insulating layer is deposited over the substrate
1
and then anisotropically etched to form second sidewall spacers
11
.
Next, a third insulating layer
12
is formed over the substrate
1
to a predetermined thickness and a second photoresist pattern
13
is formed on the third insulating layer
12
to expose the portion of the substrate
1
where the MOS transistor is formed.
Referring to
FIG. 1C
, the third insulating layer
12
is patterned by using the second photoresist pattern
13
as a mask and then the second photoresist pattern
13
is removed.
Next, a refractory metal is deposited over the substrate
1
to a predetermined thickness and then annealed to form self aligned silicide layer
14
on the gate electrode
42
and the junction regions
5
. The remaining refractory metal which is not reacted in annealing, is removed by a wet etching or a dry etching.
Referring to
FIG. 1D
, an intermediate insulating layer
15
is formed over the substrate
1
and the intermediate insulating layer
15
and the third insulating layer
12
are etched to expose the resistor
41
, junction regions
5
of the MOS transistor and the upper plate
8
of the analog capacitor
10
, thereby forming contact holes. Then, a metal interconnection layer
16
is formed over the intermediate insulating layer
15
to contact with the resistor
41
, the junction regions
5
and the upper plate
8
through the contact holes, respectively.
However, the conventional method of forming a silicide layer only over the device region become complicated with carrying out a separate additional photolithography process, thereby increasing the fabrication cost and reducing the production yield.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an analog semiconductor device and a method of fabricating the same, where a silicide layer is formed only over the portion of a resistor which is contact with a metal interconnection layer, to prevent the resistance of the resistor from varying due to the formation of the silicide layer.
Another object of the present invention is to provide a method of fabricating an analog semiconductor device, which is simplified.
In accordance with one embodiment, there is provided a semiconductor device, including: a semiconductor substrate of a first conductivity type, where isolation regions and a device region between the isolation regions are defined; field oxides formed over the respective isolation regions of the substrate; an active element formed in the device region of the substrate; a resistor having a predetermined width, formed over one of the field oxides; a dummy gate electrode formed over at the predetermined portion of the resistor, the dummy gate electrode having a width smaller than that of the resistor; an analog capacitor formed over another field oxide, the analog capacitor including lower and upper plates having predetermined widths and a dielectric film between the lower and upper plates; and metal silicide layer formed over the active element, the resistor where the dummy gate electrode is not formed, the dummy gate electrode, and the lower and upper plates of the analog capacitor, respectively.
In the embodiment, the resistor, the dummy gate electrode, and the lower and upper plates of the analog capacitor is a doped polysilicon layer.
In the embodiment, the silicide layer is a refractory metal silicide such as W, Ti, or Ta.
In the embodiment, the semiconductor device further includes: an intermediate insulating layer formed over the substrate; contact holes formed in the intermediate insulating layer over the resistor, the active element, the lower and upper plates of the analog capacitor; and metal interconnection layers formed over the intermediate insulating layer to contact with the resistor, the active element, and the lower and upper plates of the analog capacitor through the contact holes.
There is also provided a method of fabricating a semiconductor device including a resistor, a metal oxide insulator transistor, an analog capacitor, comprising the

Affiliated with

Also associated with

Rating

Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2967789