Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-02-01
2002-11-26
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185270, C365S185280
Reexamination Certificate
active
06487117
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for programming a non-volatile memory device, and more particularly, to a method for programming a NAND-type flash memory device using a bulk bias.
2. Description of the Related Art
Information stored in a non-volatile memory cell, a type of semiconductor memory device, is not erased even if power is not supplied. Accordingly, non-volatile memory devices are widely used in computers and memory cards.
Since it is easier to increase the integration degree of a NAND-type flash memory device rather than that of a NOR-type flash memory device in a non-volatile memory device, a NAND-type flash memory device is widely used in a highly integrated flash memory device.
FIG. 1
is a plan view showing part of a cell array region of a general NAND-type flash memory device.
FIG. 2
is an equivalent circuit diagram showing the cell array region of FIG.
1
.
Referring to
FIGS. 1 and 2
, active regions
1
are parallel to each other. A string selection line SSL, a plurality of word lines WL
1
, WL
2
, . . . , WLn, and a ground selection line GSL which cross the active regions
1
are parallel to one another. Contacts CT for exposing the active regions are positioned in the active regions
1
adjacent to the string selection line SSL. Bit lines BL
1
and BL
2
electrically connected to the active regions
1
through the contacts CT pass over the respective active regions
1
. Also, the active regions
1
adjacent to the ground selection line GSL are extended to the direction parallel to the ground selection line GSL to thereby operate as a common source line (CSL). String selection transistor portions SST
1
and SST
2
comprised of the string selection transistors are formed where the string selection line SSL crosses the respective active regions
1
. Cell transistor portions CT
1
and CT
2
comprised of a plurality of cell transistors are formed where the respective word lines WL
1
, WL
2
, . . . , WLn cross the respective active regions
1
. Also, ground selection transistor portions GST
1
and GST
2
comprised of ground selection transistors are formed where the ground selection line GSL crosses the respective active regions
1
.
Each cell transistor is comprised of a tunnel oxide film, a floating gate FG, an inter-poly dielectric layer, and a word line which operates as a control gate electrode, sequentially stacked on the active region
1
. Here, the floating gates FG of the respective cell transistors are formed to be separate from each other. As shown in
FIG. 1
, the string selection transistor, the plurality of cell transistors, and the ground selection transistor, which are serially arranged on the active region
1
comprise one string. Also, the respective cell transistors, the respective string selection transistors, and the respective ground selection transistors are formed as NMOS transistors and are formed in a bulk region such as a P-well region.
FIG. 3
shows voltage waveforms for explaining a method for programming a cell A among a plurality of memory cells constructing the general NAND-type flash memory device shown in
FIGS. 1 and 2
.
Referring to
FIG. 3
, the moment a power supply voltage Vcc is applied for a precharge time Tpc to the first bit line BL
1
serially connected to a first string including the cell A to be programmed, a pass voltage Vpass and a programming voltage Vpgm are sequentially applied to the second word line WL
2
corresponding to the control gate electrode of the selected cell A for the precharge time Tpc and a programming time Tpgm, respectively. The power supply voltage Vcc is continuously applied to the string selection line SSL and the second bit line BL
2
serially connected to a second string parallel to the first string for the precharge time Tpc and a programming time Tpgm. A pass voltage Vpass is applied to non-selected word lines WLns, i.e., the first word line WL
1
and the third word line WL
3
through the nth word line WLn for the precharge time Tpc and the programming time Tpgm. Also, 0 volts is applied to the ground selection line GSL, the common source line CSL, and the bulk region.
When predetermined voltages are applied to the respective control lines in order to program the selected cell A as mentioned above, the channel region of the selected cell A and the channel regions of the non-selected cells are precharged for the precharge time Tpc to a voltage close to the power supply voltage Vcc. However, charges precharged in the channel region of the selected cell A are discharged through the first bit line BL
1
which falls down to a ground potential for the programming time Tpgm. Accordingly, 0 volts are induced to the channel region of the selected cell A. As a result, the selected cell A is programmed by the programming voltage Vpgm applied to the second word line WL
2
and the channel voltage induced to 0 volts.
Meanwhile, the channel regions of the memory cells constructing the second string are electrically isolated from the second bit line BL
2
and the common source line CSL for the program time Tpgm, to thereby be floated. Therefore, a voltage increased by the programming voltage Vpgm applied to the second word line WL
2
is induced in the channel region of a non-selected cell B which shares the second word line WL
2
with the selected cell A. Accordingly, the non-selected cell B is not programmed. At this time, a voltage Vch induced in the channel region of the non-selected cell B can be represented by Equation
1
from
FIG. 4
which is a sectional view taken along the line PP′ of FIG.
1
and
FIG. 5
which is an equivalent circuit diagram of the non-selected cell B of FIG.
4
. Here, a bulk voltage Vb applied to a bulk region
10
of
FIG. 4
is 0 volts.
Vch={Ctot
÷(
Ctot+Cch
)}×
Vpgm
(b
1
)
wherein, Ctot is the total capacitance of an inter-poly dielectric layer capacitance Cipo and a tunnel oxide film capacitance Ctox, serially connected to each other. Cch is a depletion capacitance formed in the channel region. The inter-poly dielectric layer capacitance Cipo represents the capacitance of an inter-polysilicon dielectric layer IPO interposed between the floating gate FG and the second word line WL
2
of FIG.
4
. The tunnel oxide film capacitance Ctox represents the capacitance of a tunnel oxide film Tox interposed between the floating gate FG and the bulk region
10
of FIG.
4
.
Referring to
FIG. 4
again, a field oxide film Fox operates as an isolation film between the selected cell A and the non-selected cell B. Therefore, a parasitic field transistor is formed between the selected cell A and the non-selected cell B. There is a high probability that the parasitic field transistor is turned on as the channel voltage Vch of the non-selected cell B is higher when the selected cell A is programmed. In addition, it is easier for the parasitic field transistor to turn on as the thickness and the width of the field oxide film Fox are reduced. Accordingly, when the parasitic field transistor is turned on, since undesired leakage current I
L
flows from the channel region of the non-selected cell B to the channel region of the selected cell A through the surface of the bulk region
10
under the field oxide film Fox, the channel voltage Vch of the non-selected cell B is lowered. As a result, the non-selected cell B is programmed.
As mentioned above, according to the conventional technology, the non-selected cell may be programmed since the parasitic field transistor between the selected cell and the non-selected cell is easily turned on. In particular, when the width and the thickness of the field oxide film are reduced in order to realize a highly integrated NAND-type flash memory device, the non-selected cell is much more easily programmed.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a method for programming a NAND-type flash memory device by which it is possible to prevent a non-selected cell from being programmed though the thickness
Choi Jeong-hyuk
Shin Yun-seung
Cantor & Colburn LLP
Mai Son
Samsung Electronics Co,. Ltd.
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