Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-01-07
2002-02-12
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S342000, C257S413000
Reexamination Certificate
active
06346727
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having optimized two-dimensional arrays of double diffused MOS field effect transistor cells having a reduced ON-resistance between source and drain, a reduced threshold voltage and an increased source-drain withstand voltage as well as a method of optimization of two-dimensional arrays of double diffused MOS field effect transistor cells for obtaining possible reductions in channel resistance and threshold voltage of the double diffused MOS field effect transistor cells.
FIGS. 1A through 1G
are fragmentary cross sectional elevation views illustrative of a method of forming a double diffused MOS field effect transistor over a semiconductor substrate.
With reference to
FIG. 1A
, a gate oxide film
2
having a thickness of 20-200 nanometers is formed on an n-type semiconductor substrate
With reference to
FIG. 1B
, a gate polysilicon layer
3
is deposited on the gate oxide film
2
by a chemical vapor deposition method so that the gate polysilicon layer
3
has a thickness of 300-600 nanometers. The gate polysilicon layer
3
is then doped with phosphorus to reduce a resistivity thereof.
With reference to
FIG. 1C
, the phosphorus-doped gate polysilicon layer
3
and the gate oxide film
2
are patterned by a photolithography technique, thereby to form a gate electrode
3
so that a predetermined region of the n-type semiconductor substrate
1
is shown.
With reference to
FIG. 1D
, an p-type impurity is ion-implanted into the predetermined region of the n-type semiconductor substrate
1
so that a p-type base region
4
is selectively formed in an upper region of the n-type semiconductor substrate
1
.
With reference to
FIG. 1E
, an n-type impurity is selectively ion-implanted into selected regions of the p-type base region
4
so that n+-type source regions
5
are selectively formed in selected upper regions of the p-type base region
4
.
With reference to
FIG. 1F
, an inter-layer insulator
6
having a thickness of 300-1500 nanometers is entirely formed over the gate electrode
3
, the n+-type source regions
5
and the p-type base region
4
. A contact hole is formed in the inter-layer insulator
6
so that the contact hole is positioned over inside half of each of the n+-type source regions
5
and the p-type base region
4
.
With reference to
FIG. 1G
, an aluminum electrode
7
having a thickness of 1-3 micrometers is entirely deposited over the inter-layer insulator
6
, the over inside half of each of the n+-type source regions
5
and the p-type base region
4
, so that the aluminum electrode layer
7
is made into contact with the n+-type source regions
5
. A drain electrode
8
is formed on a bottom surface of the n-type semiconductor substrate
1
.
FIG. 2A
is a fragmentary plane view illustrative of a first conventional two-dimensional array of a plurality of double diffused MOS field effect transistors over a semiconductor substrate.
FIG. 2B
is a fragmentary cross sectional elevation view illustrative of a semiconductor device having the first conventional two-dimensional array of a plurality of double diffused MOS field effect transistors, taken along an A-A′ line of
FIG. 2A
With reference to
FIG. 2A
, a plurality of square-shaped double diffused MOS field effect transistor cells are aligned in matrix, wherein the shape of each of the square-shaped double diffused MOS field effect transistor cells is defined by a boundary line between outside edges of the source region
5
and channel regions
14
. Each of the square-shaped double diffused MOS field effect transistor cells is surrounded by a square-frame shaped channel region
14
. A square-shaped boundary broken line
9
corresponds to the outside edge of the square-frame shaped channel region
14
or the outside edge of the base region
4
. Adjacent two of the square-shaped double diffused MOS field effect transistor cells are distanced from each other.
With reference to
FIG. 2B
, the p-type base regions
4
are selectively formed in selected upper regions of the n-type semiconductor substrate
1
. The n+-type source regions
5
are selectively formed in selected upper regions of the p-type base regions
4
. Each of the square-frame shaped channel regions
14
is defined between the outside edges of the n+-type source regions
5
and the outside edge of the p-type base region
4
. The gate oxide film
2
is selectively formed on the n-type semiconductor substrate
1
and on the square-frame shaped channel regions
14
. The phosphorus doped polysilicon gate electrode
3
is provided on the gate oxide film
2
. The inter-layer insulator
6
is provided, which covers the phosphorus doped polysilicon gate electrode
3
and the outside half regions of the n+-type source regions
5
. The aluminum electrode layer
7
is provided which entirely extends over the inter-layer insulator
6
and inside half regions of the n+-type source regions
5
. The drain electrode
8
is provided on the bottom surface of the n-type semiconductor substrate
1
.
FIG. 3A
is a fragmentary plane view illustrative of a second conventional two-dimensional array of a plurality of double diffused MOS field effect transistors over a semiconductor substrate.
FIG. 3B
is a fragmentary cross sectional elevation view illustrative of a semiconductor device having the second conventional two-dimensional array of a plurality of double diffused MOS field effect transistors, taken along an A-A′ line of FIG.
3
A.
With reference to
FIG. 3A
, a plurality of circular-shaped double diffused MOS field effect transistor cells are aligned in two dimensional staggered alignment, wherein the shape of each of the circular-shaped double diffused MOS field effect transistor cells is defined by a boundary circular line between outside edges of the annular-shaped source region
5
and circular-frame shaped channel regions
14
. Each of the circular-shaped double diffused MOS field effect transistor cells is surrounded by the circular-frame shaped channel region
14
. A circular-shaped boundary broken line
9
corresponds to the outside edge of the circular-frame shaped channel region
14
or the outside edge of the base region
4
. Adjacent two of the circular-shaped double diffused MOS field effect transistor cells are distanced from each other.
With reference to
FIG. 3B
, the p-type base regions
4
are selectively formed in selected upper regions of the n-type semiconductor substrate
1
. The n+-type source regions
5
are selectively formed in selected upper regions of the p-type base regions
4
. Each of the circular-frame shaped channel regions
14
is defined between the outside edges of the n+-type source regions
5
and the outside edge of the p-type base region
4
. The gate oxide film
2
is selectively formed on the n-type semiconductor substrate
1
and on the circular-frame shaped channel regions
14
. The phosphorus doped polysilicon gate electrode
3
is provided on the gate oxide film
2
. The inter-layer insulator
6
is provided, which covers the phosphorus doped polysilicon gate electrode
3
and the outside half regions of the n+-type source regions
5
. The aluminum electrode layer
7
is provided which entirely extends over the inter-layer insulator
6
and inside half regions of the n+-type source regions
5
. The drain electrode
8
is provided on the bottom surface of the n-type semiconductor substrate
1
.
FIG. 4A
is a fragmentary plane view illustrative of a third conventional two-dimensional array of a plurality of double diffused MOS field effect transistors over a semiconductor substrate.
FIG. 4B
is a fragmentary cross sectional elevation view illustrative of a semiconductor device having the third conventional two-dimensional array of a plurality of double diffused MOS field effect transistors, taken along an A-A′ line of FIG.
4
A.
FIG. 4C
is a fragmentary cross sectional elevation view illustrative of
NEC Corporation
Prenty Mark V.
Young & Thompson
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