Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-05-10
2002-08-27
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S638000, C438S675000
Reexamination Certificate
active
06440842
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a dual damascene structure on a semiconductor wafer.
2. Description of the Prior Art
A dual damascene process is a method of forming a conductive wire coupled with a via plug. The dual damascene structure is used to connect devices and wires in a semiconductor wafer and is insulated from other devices by an inter-layer dielectrics (ILD) around it. At the end of the dual damascene process, a chemical mechanical polishing (CMP) process is always performed to planarize the surface of the semiconductor wafer so that subsequent deposition and photolithographic processes perform well on the wafer, resulting in good multilevel interconnects being formed. As a result, the dual damascene structure is widely used in the manufacturing of integrated circuits. As integrated circuit technology advances, improving the yield of the dual damascene structure is an important challenge in the manufacturing of integrated circuits at the present time.
Please refer to
FIG. 1
to FIG.
6
.
FIG. 1
to
FIG. 6
are schematic diagrams of a process of forming a dual damascene structure
42
on a semiconductor wafer
10
according to the prior art. As shown in FIG. l, the semiconductor wafer
10
comprises a substrate
12
, a conductive layer
14
positioned on a predetermined area of the substrate
12
, a first inter layer dielectric (ILD)
16
formed of silicon oxide and positioned on the substrate
12
and the conductive layer
14
, a silicon nitride (SiN) layer
18
positioned on the ILD
16
, and a second inter layer dielectric (ILD)
20
formed of silicon oxide and positioned on the silicon nitride layer,
18
. The ILD
16
, the silicon nitride layer
18
and the ILD
20
are deposited serially using plasma-enhanced chemical vapor deposition (PECVD).
In the prior art method of forming the dual damascene structure
42
, a lithographic process is performed first to form a photoresist layer
22
evenly on the ILD
20
with an opening
24
positioned above the conductive layer
14
, which extends down to the ILD
20
. The opening
24
is used to define the via pattern. As shown in
FIG. 2
, an anisotropic dry-etching process is then performed along the opening
24
to vertically remove the ILD
20
and the silicon nitride layer
18
positioned under the opening
24
down to the ILD
16
, which forms a hole
26
. Then, a resist stripping process is performed to completely remove the first photoresist layer
22
.
As shown in
FIG. 3
, a lithographic process is performed again to form a photoresist layer
28
evenly on the ILD
20
with two line-shaped openings
30
in the photoresist layer
28
so as to define the wiring line pattern for connecting transistors. As shown in
FIG. 4
, a dry-etching process is then performed along the line-shaped openings
30
and hole
26
to vertically remove the ILD
20
and ILD
16
positioned under the openings
30
and the hole
26
down to the silicon nitride layer
18
and the substrate
12
, so as to form two line-shaped recesses
32
and a via hole
34
.
As shown in
FIG. 5
, the photoresist layer
28
is then removed completely. A metallic layer
36
is deposited on the semiconductor wafer
10
so as to fill the line-shaped recesses
32
and the via hole
34
to form conductive wires
38
and a via plug
40
. As shown in
FIG. 6
, a chemical mechanical polishing (CMP) process is employed to remove the metallic layer
36
positioned on the ILD
20
and to align the upper surface of the conductive wire
38
with the surface of the ILD
20
, completing the dual damascene structure
42
.
In the prior art method of forming the dual damascene structure
42
, the width (W) at the bottom of the via hole
34
is much smaller than the depth of the hole (H), so the via hole
34
has a high aspect ratio. When the via hole
34
is filled with the metallic layer
36
, the metallic layer
36
will overhang from the upper corners of the via hole
34
and further restrict the hole
34
, causing voids
44
to form inside the via plug
40
. The resistance of the via plug
40
will increase because of the voids
44
in the via plug
40
, resulting in an unstable electrical current in the dual damascene structure
42
, which can affect the electrical performance of an integrated circuit. Furthermore, because of the voids
44
inside the via plug
40
, the structure of the dual damascene may be weakened and so more easily damaged in subsequent processes.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a dual damascene structure on a semiconductor wafer for preventing the formation of voids in the via plug of the dual damascene structure.
The method of present invention is to first form a sacrificial layer on the surface of the substrate. Then, a patterned first photoresist layer is formed on the surface of the sacrificial layer covering, the conductive area, followed by removal of the sacrificial layer not covered by the first photoresist layer. Thereafter, a dielectric layer is formed on the surface of the substrate, and the second photoresist layer is formed on the surface of the dielectric layer. A line-shaped opening is formed in the second photoresist layer positioned above the remaining sacrificial layer. Portions of the dielectric layer are etched through the line-shaped opening for forming a line-shaped recess, followed by the second photoresist layer and the remaining sacrificial layer being completely removed, for forming a plug hole in the bottom of the line-shaped recess. Thereafter, a metal layer is formed on the surface of the semiconductor wafer filling the line-shaped recess and the plug hole for forming a metal conductive wire and a conductive plug in the line-shaped recess and in the plug hole. The metal conductive wire coupled with the conductive plug is defined as a dual damascene structure. Finally, the metal layer positioned on the top surface of the dielectric layer is removed to finish the process of the dual damascene structure.
The present invention method of forming a dual damascene structure can form a via plug with a fine structure and prevent the formation of voids in the plug hole when filling the metal layer in the plug hole by a prior art method.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
REFERENCES:
patent: 6033977 (2000-03-01), Gutsche et al.
patent: 6174804 (2001-01-01), Hsu
patent: 6284641 (2001-09-01), Parekh
patent: 6309957 (2001-10-01), Tu et al.
A Kajita et al., “A Fully Integrated Pillar Process for High Performance Cu Interconnect Scheme,” Proceedings of the 1999 IEEE International Conference on Interconnect Technology, May 1999, pp. 259-261.
Chaudhuri Olik
Hsu Winston
Macronix International Co. Ltd.
Smoot Stephen W.
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