Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-03-31
2002-06-25
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S357000, C257S371000
Reexamination Certificate
active
06410964
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device using MOS transistors and a method of manufacturing the semiconductor device, and more particularly to a semiconductor device having a structure for protecting gate oxide films thereof from surge and a method of manufacturing the semiconductor device.
Conventionally, in the MOS structure of the MOS transistor, when the surge is supplied directly, the gate oxide film is broken or the property of the film is degraded. Therefore, the transistors of input buffers and output buffers having the possibility that the surge is supplied directly from the outside of LSIs provided with electrostatic protective elements specifically. On the other hand, although the specific electrostatic protective device is not provided on the transistors of the internal circuits having no possibility that the surge from the outside is supplied directly, the PN diode formed in a drain diffused layer and a well region of the transistor of a preceding stage acts as a protective element.
In the interim, there are manufacturing processes using plasma, damage is given to the gate oxide film of the MOS transistor in this manufacturing process, whereby the reliability of the MOS transistor can be seriously affected. For example, in etching process of aluminum used as wiring, for the gate oxide film of the independent gate electrode to which no protective element is connected, an electric stress is applied at overetching. This electric charge causes the capture of charge in an interface between the gate oxide film and silicon and generation of interface energy levels, so that degradation of the reliability such as characteristic fluctuation of VT and Gm or the like and degradation of hot carrier device life time or the like are caused. Although the major portion of the characteristic fluctuation is recovered by hydrogen alloy in manufacturing process, a time period and temperature of the hydrogen alloy are limited to effects of an influence on wiring material such as stress migration. Accordingly, it becomes more difficult that the characteristic fluctuation of the MOS transistor caused by the plasma damage is recovered perfectly, as the damage becomes larger. Furthermore, since the neutral capture energy levels are left even after performing of hydrogen alloy, the degradation of the hot carrier device life time has become serious trouble points.
In the structure of the conventional semiconductor device, it is impossible to avoid the problem that the gate oxide film is damaged in the plasma process. In addition, since the number of wiring thereof tends to increase by growth of the LSIs in performance, the gate oxide film tends to be exposed to the plasma process. Moreover, it is the realities that an electric stress tends to be increased by forming or the like of etching and isolation between layers utilizing a high density plasma source due to micronization of wiring and improvement of planarization.
On the other hand, thinning the gate oxide film is essentially required for speeding up the MOS transistor. As a result, a new problem of breakdown of the oxide film during the plasma process is caused, since the characteristic fluctuation and degradation of reliability for the electric stress not only become more significant, but also intrinsic breakdown voltage of the gate oxide film reduces proportional to the thickness of the gate oxide film.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a semiconductor device capable of preventing gate oxide film from damage by plasma process and a method of manufacturing the semiconductor device.
Other objects of this invention will become clear as the description proceeds.
According to an aspect of this invention, a semiconductor device and a method of manufacturing the semiconductor device are obtained as follows:
(1) A semiconductor device having MOS transistors, said device characterized in that protective elements are connected to the independent gate electrode through the wiring layer of the lowest layer.
(2) A semiconductor device according to the embodiment 1 characterized in that said wiring layer of the lowest layer is constituted by the gate electrode.
(3) A semiconductor device according to the embodiment 2 characterized in that said protective elements are constituted by the PN diodes comprising:
a second conduction type well in which a first conduction type MOS transistor is formed, and a first conduction type diffused layer region formed by impurity diffusion from said gate electrode within said second conduction type well.
(4) A semiconductor device according to any one of the embodiment 1 to the embodiment 3 characterized in that said protective elements are formed in only either region of the first or the second conduction type regions.
(5) A semiconductor device according to any one of the embodiment 2 to the embodiment 4 characterized in that said protective elements are formed directly below a lead gate electrode.
(6) A method for manufacturing the semiconductor device of any one of the embodiment 1 to the embodiment 5 characterized in that a process for forming said protective element has been completed at the point of the time that the formation of the source drain is completed.
REFERENCES:
patent: 3712995 (1973-01-01), Steudel
patent: 4720737 (1988-01-01), Shirato
patent: 5519242 (1996-05-01), Avery
patent: 5567968 (1996-10-01), Tsuruta et al.
patent: 5828119 (1998-10-01), Katsube
patent: 2-78230 (1990-03-01), None
patent: 5-291568 (1993-11-01), None
patent: 6-232360 (1994-08-01), None
Crane Sara
NEC Corporation
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