Method of forming high density EEPROM cell

Details Method of forming high density EEPROM cell Method of forming high density EEPROM cell

2001-05-14

2002-12-24

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S257000

Reexamination Certificate

active

06498084

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to semiconductor processing, and in particular, to a new and improved electrically erasable programmable read only memory (EEPROM) cell and method therefor.
BACKGROUND OF THE INVENTION
A typical electrically erasable programmable read only memory (EEPROM) cell comprises a p-substrate with an n-well having spaced apart drain and source regions. A current conducting channel is defined between the drain and source regions. A control gate is situated over a first portion of the channel and separated therefrom by a thin oxide. A floating gate is situated over a second portion of the channel and separated therefrom by a thin oxide. This thin oxide that separates the floating gate from the channel is typically termed in the art as the tunnel oxide or tunnel window, since this is the material that electrons tunnel through in programming the memory cell.
Typically, the performance of the typical memory cell depends on the alignment of the tunnel window with respect to the control gate. If the tunnel window is misaligned with the control gate, the performance of the memory cell may not meet the desired specification. Thus, a memory cell susceptible to misalignment errors generally translates into a relatively low yield. The susceptibility to misalignment errors of the tunnel window to the control gate may also affect the scalability of the device. If a memory cell is susceptible to misalignment errors, it generally becomes more difficult to scale the memory cell for other manufacturing technology.
Thus, there is a need for a EEPROM memory cell which has a tunnel window self aligned to the control gate and drain and source regions that are self-aligned with the control gate to improve the yield of EEPROM memory arrays and their scalability. In addition, there is a need for a tunnel window that can be made smaller for increasing the density of memory arrays. Such needs and others are met with the EEPROM memory cell and method therefor in accordance with the invention.
SUMMARY OF THE INVENTION
An aspect of the invention relates to a new and improved electrically erasable programmable read only memory (EEPROM) cell. The memory cell comprises a substrate with a well having drain and source regions a channel therebetween. The memory cell further comprises a control gate with a first portion overlying a first region of the channel adjacent to the drain region and a second portion overlying a second region of the channel adjacent to the source region. The memory cell includes first and second dielectrics to respectfully separate the first and second control gate portions from the first and second regions of the channel.
The memory cell of the invention further comprises a floating gate with a first portion overlying the first control gate portion, a second portion overlying a third region of the channel between the first and second regions, and a third portion overlying the second control gate portion. The floating gate also includes a fourth portion that extends generally vertical from the first portion to the second portion of the floating gate, and a fifth portion that extends generally vertical from the second portion to the third portion of the floating gate.
The memory cell includes a third dielectric that separates the second floating gate portion from the third region of the channel, a fourth dielectric that separates the first control gate portion from the first floating gate portion, and a fifth dielectric that separates the second control gate portion from the third floating gate portion. In addition, the memory cell comprises a first dielectric spacer that separates the first control gate portion from the fourth floating gate portion, and a second dielectric spacer that separates the second control gate portion from the fifth floating gate portion.
In the exemplary embodiment, the floating and control gates are formed of doped poly crystalline silicon (“polysilicon”), the first, second and third dielectrics are formed of thermally-grown silicon dioxide (SiO
2
), the fourth and fifth dielectrics are formed of an oxide-nitride-oxide (ONO) stack or optionally an oxide-nitride-oxide-nitride (ONON) stack, and the first and second dielectric spacers are formed of a thermally-grown silicon dioxide (SiO
2
) sub-spacer and a silicon nitride (Si
3
N
4
) sub-spacer. The substrate may be doped with p-type dopant, the well may be doped with n-type dopant, and the drain and source region may be doped with p-type dopant. Alternatively, the substrate may be doped with n-type dopant, the well may be doped with p-type dopant, and the drain and source region may be doped with n-type dopant.
Another aspect of the invention relates to a method of forming an EEPROM memory cell. Other aspects, features and techniques of the invention will become apparent to one skilled in the relevant art in view of the following detailed description of the invention.


REFERENCES:
patent: 5429971 (1995-07-01), Yang
patent: 5714412 (1998-02-01), Liang et al.
patent: 5830794 (1998-11-01), Kusunoki et al.
patent: 5986931 (1999-11-01), Caywood

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