Sequence circuit and semiconductor device using sequence...

Details Sequence circuit and semiconductor device using sequence... Sequence circuit and semiconductor device using sequence...

2001-10-29

2002-11-19

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including signal clamping

Reexamination Certificate

active

06483756

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sequence circuit and a semiconductor device. More particularly, the present invention relates to a sequence circuit controlling start up of a power-supply circuit, and a semiconductor device using the sequence circuit.
2. Description of the Related Art
A semiconductor device using a layer-built cell capacitor and a negative word-line resetting system generates a plurality of power sources from an internal step-down power source, and uses the plurality of power sources, for example. A sequence circuit shown in
FIG. 1
controls start up of a power-supply circuit generating the plurality of power sources from the internal step-down power source.
FIG. 1
shows an example of a structure of a sequence circuit
1
controlling start up of a power-supply circuit. The sequence circuit
1
shown in
FIG. 1
controls start up of a power-supply circuit including a Vbl/Vcp generating unit
11
and a Vnn generating unit
12
, and includes a Vii voltage-detecting unit
10
and a sequencer
13
.
The Vbl/Vcp generating unit
11
generates a bit-line power-supply voltage Vbl and a cell-plate power-supply voltage Vcp. The Vnn generating unit
12
generates a negative power-supply voltage Vnn. The Vii voltage-detecting unit
10
detects an internal step-down power-supply voltage Vii. Additionally, the sequencer
13
controls a start-up order of a power-supply-voltage-generating unit such as the Vnn generating unit
12
. The sequencer
13
includes a plurality of sequencers
13
-
1
,
13
-
2
and so on, in accordance with the number of the power-supply-voltage-generating units whose start-up orders are controlled.
The sequencer
13
is reset initially at start up. The Vii voltage-detecting unit
10
detects the internal step-down power-supply voltage Vii, and supplies a signal “Vii_ok” to the sequencer
13
-
1
if the voltage Vii rises to a fixed voltage. The sequencer
13
-
1
supplies a signal “act” to the Vbl/Vcp generating unit
11
and the Vnn generating unit
12
if the signal Vii_ok is supplied from the Vii voltage-detecting unit
10
.
The Vbl/Vcp generating unit
11
starts generating the bit-line power-supply voltage Vbl and the cell-plate power-supply voltage Vcp, if the signal “act” is supplied from the sequencer
13
-
1
. Additionally, the Vnn generating unit
12
starts generating the negative power-supply voltage Vnn, if the signal “act” is supplied from the sequencer
13
-
1
. The Vnn generating unit
12
supplies a signal “Vnn_ok” to the sequencer
13
-
1
, if the negative power-supply voltage Vnn rises to a fixed voltage. If the signal “Vnn_ok” is supplied from the Vnn generating unit
12
, the sequencer
13
-
1
supplies a signal “Sq.
1
_ok” to the sequencer
13
-
2
.
As described above, a related-art sequence circuit operates the Vbl/Vcp generating unit
11
and the Vnn generating unit
12
concurrently.
FIG. 2
is a circuit diagram showing an example of capacity coupling among a word line, a bit line and a cell plate. In a layer-built cell capacitor shown in
FIG. 2
, a word line WL is coupled with a bit line BL and a cell plate CP with a large capacity. The negative word-line resetting system resetting a word line to a negative voltage while being inactive needs the negative power-supply voltage Vnn.
Strong capacity coupling is performed among the word line WL, the bit line BL and the cell plate CP, since voltages of the word line WL, the bit line BL and the cell plate CP are set to the negative power-supply voltage Vnn, the bit-line power-supply voltage Vbl and the cell-plate power-supply voltage Vcp, respectively, at start up.
FIG. 3
is a diagram showing an example of voltage changes of the negative power-supply voltage Vnn, the bit-line power-supply voltage Vbl and the cell-plate power-supply voltage Vcp at a time of starting up a power source. As shown in
FIG. 3
, if the bit-line power-supply voltage Vbl and the cell-plate power-supply voltage Vcp rise at the time of starting up the power source, the negative power-supply voltage Vnn is raised for a certain period even if the Vnn generating unit
12
is operating. Accordingly, the Vnn generating unit
12
needs to lower the negative power-supply voltage Vnn raised as described above, and, thus, a start-up time is extended.
Further, an increase in the negative power-supply voltage Vnn has a possibility to cause a through current shown in
FIG. 4
, latch up and the like.
FIG. 4
is a circuit diagram showing an example of a word-line driving circuit. The negative word-line resetting system lowers a voltage of a sub word line to the negative power-supply voltage Vnn, after lowering the voltage of the sub word line to a ground voltage Vss.
An NMOS (Negative Metal-Oxide Semiconductor) transistor
15
shown in
FIG. 4
is a driver that lowers the voltage of the sub word line to the ground voltage Vss at the time of starting up the power source. A gate, a source and a drain of the NMOS transistor
15
are connected to the negative power-supply voltage Vnn, the ground voltage Vss and the internal step-down power-supply voltage Vii, respectively. A through current is generated from the internal step-down power-supply voltage Vii to the ground voltage Vss because of a rise in the negative power-supply voltage Vnn. For example, tens of milliamperes (mA) of a through current is generated in an entire 128M-bit chip.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a sequence circuit and a semiconductor device employing the sequence circuit. A more particular object of the present invention is to provide a sequence circuit that can reduce a consumed current by avoiding a rise in a negative power-supply voltage used for resetting a word line at a time of starting up a power source, and a semiconductor device employing the sequence circuit.
The above-described object of the present invention is achieved by a sequence circuit that controls a start-up order of a power-supply circuit, including a first circuit that detects a first power-supply voltage charging a capacitor of a memory cell or a bit line; a second circuit that clamps a second power-supply voltage resetting a word line, to a first fixed voltage, until the first power-supply voltage reaches a second fixed voltage; and a third circuit that cancels clamping the second power-supply voltage after the first power-supply voltage reaches the second fixed voltage, and, then, generates the second power-supply voltage.
The above-described object of the present invention is also achieved by a semiconductor device, including a word line that is reset to a negative voltage when the word line is unselected; and a sequence circuit that clamps the word line to a first fixed voltage until a fixed power-supply voltage supplied to a memory cell reaches a second fixed voltage, at a time of starting up power supply.
Since the sequence circuit clamps the word line to the first fixed voltage such as a ground-level voltage, until the fixed power-supply voltage supplied to the memory cell reaches the second fixed voltage, at the time of starting up the power supply, the semiconductor device can prevent a negative power-supply voltage used for resetting the word line from rising. Consequently, the semiconductor device can reduce consumed energy.


REFERENCES:
patent: 5864507 (1999-01-01), Hawkins et al.

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