Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-08-04
2002-12-10
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S396000, C257S408000, C257S412000
Reexamination Certificate
active
06492690
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which a plurality of types of transistors are formed within one chip and a method of manufacturing such a semiconductor device.
2. Description of the Background Art
As a semiconductor device in which a plurality of types of transistors (e.g., transistors having different required specifications from each other) are formed within one chip, the following four conventional examples will be described.
FIRST CONVENTIONAL EXAMPLE
Overall Structure of DRAM
First, as a first conventional example, a structure of a DRAM
600
in which a plurality of types of transistors are formed and a method of manufacturing the same will be described. The structure of the DRAM
600
(i.e., cell structure) is shown in FIG.
66
.
The DRAM
600
includes not only a memory cell array portion
601
for storing data, but also a peripheral circuit portion (i.e., an address buffer
602
, an X decoder
603
, a Y decoder
604
, a row/column clock portion
605
, an I/O pass portion
606
, a refresh portion
607
), a sense amplifier portion
608
, etc.
Although any these portions are formed by transistors, characteristics required for these portions are different from each other. For instance, the memory cell array portion
601
only allows a low leak current, in order to prevent disappearance of data because of a leak current. Meanwhile, a high amount of current is demanded in the peripheral circuit portion so as to enable operations at a high speed. Further, to distinguish a high level from a low level, the sense amplifier portion
608
must operate at a voltage which is half that of the high level, for example. To this end, a transistor which is used for the sense amplifier portion
608
must operate at a low voltage. In short, a plurality of types of transistors which have different characteristics from each other are needed within the DRAM which is formed as one chip.
Comparing threshold values, for instance, a threshold value for a transistor of the memory cell array portion is about
1
V and a threshold value for transistors of the peripheral circuit portions are about 0.8V, while a threshold value for the transistor of the sense amplifier portion must be suppressed as low as 0.4V.
Structures Of The Respective Transistors
A conventional approach for forming these transistors which have different characteristics from each other within one chip is to change an impurity profile of a channel dope layer in accordance with a transistor. In the following, an example where an impurity concentration of a channel dope is changed in accordance with a transistor will be described.
FIG. 67
shows (in a partial view) an example of a structure of a DRAM which is fabricated by a conventional manufacturing method. Cross sections of N-channel MOS transistors T
1
to T
3
which are used for the sense amplifier portion, the peripheral circuit portion, and the memory cell array portion are shown.
In
FIG. 67
, the N-channel MOS transistors T
1
to T
3
are formed within a P-type well layer
101
which is formed on the same semiconductor substrate
1
(of the P-type). The well layer
101
is element-separated by a channel cut layer
102
and a LOCOS layer
2
in such a manner that the N-channel MOS transistors Ti to T
3
are formed in regions which are created by element separation.
The N-channel MOS transistor T
1
of the sense amplifier portion comprises a pair of source/drain layers
106
formed within the well layer
101
independently of each other but parallel to each other and a pair of low dope drain layers (hereinafter “LDD layers”)
107
formed adjacent ts edge portions facing each other of the source/drain layers
106
.
The gate oxide film
3
is formed on the LDD layers
107
, and a gate electrode
4
is formed on the gate oxide film
3
. A side wall oxide film
5
is formed on a side surface of the gate oxide film
3
and the gate electrode
4
. Within the well layer
101
under the gate electrode
4
, a channel dope layer
103
is formed.
The N-channel MOS transistor T
2
of the peripheral circuit portion comprises a pair of source/drain layers
106
formed within the well layer
101
independently of each other but parallel to each other and a pair of LDD layers
107
.
The gate oxide film
3
is formed on the LDD layers
107
, and a gate electrode
4
is formed on the gate oxide film
3
. The side wall oxide film
5
is formed on a side surface of the gate oxide film
3
and the gate electrode
4
. Within the well layer
101
under the gate electrode
4
, a channel dope layer
104
is formed.
The N-channel MOS transistor T
3
of the memory cell array portion comprises a pair of source/drain layers
106
formed within the well layer
101
independently of each other but parallel to each other and a pair of LDD layers
107
.
A gate oxide film
3
is formed on the source/drain layers
106
and the LDD layers
107
, and a gate electrode
4
is formed on the gate oxide film
3
. The side wall oxide film
5
is formed on a side surface of the gate oxide film
3
and the gate electrode
4
. Within the well layer
101
under the gate electrode
4
, a channel dope layer
105
is formed. The memory cell array portion has a gate array structure in which adjacent gates share one source/drain layer
106
. Such structures are arranged successively.
Table 1 shows figures regarding the structures of the N-channel MOS transistors T
1
to T
3
.
TABLE 1
SENSE AMPLIFIER
PERIPHERAL CIRCUIT
MEMORY CELL ARRAY
PORTION (T1)
PORTION (T2)
PORTION (T3)
FIELD OXIDE FILM THICKNESS
4000 Å
4000 Å
4000 Å
GATE OXIDE FILM THICKNESS
100 Å
100 Å
100 Å
GATE ELECTRODE FILM THICKNESS
2000 Å
2000 Å
2000 Å
GATE IMPURITY CONCENTRATION
5 × 10
20
/cm
3
5 × 10
20
/cm
3
5 × 10
20
/cm
3
SIDE WALL
1000 Å
1000 Å
1000 Å
WELL
B 700 keV 1 × 10
13
/cm
2
B 700 keV 1 × 10
13
/cm
2
B 700 keV 1 × 10
13
/cm
2
CHANNEL CUT
B 130 keV 5 × 10
12
/cm
2
B 130 keV 5 × 10
12
/cm
2
B 130 keV 5 × 10
12
/cm
2
CHANNEL DOPE
B 50 keV 1 × 10
12
/cm
2
B 50 keV 3 × 10
12
/cm
2
B 50 keV 5 × 10
12
/cm
2
LDD
As 30 keV 1 × 10
13
/cm
2
As 30 keV 1 × 10
13
/cm
2
As 30 keV 1 × 10
13
/cm
2
SOURCE/DRAIN
As 50 keV 5 × 10
15
/cm
2
As 50 keV 5 × 10
15
/cm
2
As 50 keV 5 × 10
15
/cm
2
THERMAL PROCESSING
850° C. 60 min
In Table 1, impurity dose for forming the channel dope layers of the N-channel MOS transistors T
1
, T
2
and T
3
are 1×10
12
/cm
2
, 3×10
12
/cm
2
and 5×10
2
/cm
2
, respectively. Boron (B) is implanted as an impurity for either layers with the implantation energy of 50 keV.
FIG. 68
shows impurity profiles of the N-channel MOS transistors T
1
, T
7
and T
3
forming the sense amplifier portion, the peripheral circuit portion and the memory cell array portion, all of which are shown in
FIG. 67
, taken at cross sectional portions along A-A′ line, B-B′ line and C-C′ line, respectively.
In
FIG. 68
, a position (i.e., depth) in a cross sectional direction is shown along a horizontal axis and an impurity concentration is shown along a vertical axis. There are the gate electrode (polysilicon layer), the gate oxide film (SiO
2
layer) and the well layer (bulk silicon layer) in this order along the horizontal axis from the left-hand side.
As shown in Table
1
, the impurity concentration in the gate electrode stays uniformly at the same quantity among any transistors, and therefore, the A-A′ line, the B-B′ line and the C-C′ line are one atop the other and shown as overlapping straight lsnes. On the other hand, in the well layer, as described earlier, the channel dose is smaller for a transistor which requires a lower threshold value (i.e., T
1
<T
2
<T
3
), and therefore, the impurity concentration is low at an interface
Maeda Shigenobu
Maegawa Shigeto
Okumura Yoshinori
Ueno Shuichi
LandOfFree
Semiconductor device having control electrodes with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having control electrodes with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having control electrodes with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2965464