Source/drain formation with sub-amorphizing implantation

Details Source/drain formation with sub-amorphizing implantation Source/drain formation with sub-amorphizing implantation

2001-06-29

2002-11-05

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S301000, C438S305000, C257S344000

Reexamination Certificate

active

06475885

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods of fabricating source/drain structures.
2. Description of the Related Art
A typical field effect transistor consists of a gate electrode positioned on a semiconductor substrate and a gate dielectric layer interposed between the gate electrode and the substrate. Source/drain impurity regions are formed in the substrate on either side of the gate electrode. The lateral separation between the source/drain regions defines the channel region for the transistor. Changes in the electric field emitted from the gate electrode alter the conductivity of the substrate in the channel region and thereby turn the transistor on or off.
Many types of field effect transistors are fabricated with source/drain regions that include lightly doped drain (“LDD”) or source/drain extension region structures. The LDD structures extend beneath the gate electrode to reduce hot carrier effects through a reduction in the peak electric field. While helping to eliminate hot carrier effects, LDD regions nevertheless increase the parasitic resistance of the transistor by providing a high resistance path between the source and the drain.
The conventional fabrication of a source/drain region involves the introduction of conductivity altering impurities into the substrate, normally by ion implantation, followed by an activation anneal. The anneal is designed to disperse the implanted impurities as well as repair crystalline damage inflicted on the substrate by the implantation process. A pre-amorphization technique is frequently used to improve the activation of the source/drain regions and therefore improve the performance of the transistor. A typical pre-amorphization process involves implanting the substrate in the vicinity of the source/drain regions with a neutral species, such as silicon or germanium. The dosage of the implant is set high enough to ensure amorphization. During the subsequent activation anneal, the silicon within the amorphous region regrows into a generally defect free region with good activation. However, the conventional pre-amorphization approach is not without drawbacks. The end-of-range damage is frequently not completely removed during the anneal since the thermal budget for small geometry devices is quite low. Thus, the activation anneal may not be performed for a long enough duration in order to remove the end-of-range damage. The unannealed damage beyond the amorphous/crystalline interface increases the diode junction leakage, which may be undesirable for some applications.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a method of processing a semiconductor workpiece is provided that includes implanting a neutral ion species into the substrate at a sub-amorphizing dosage to provide a plurality of interstitials. A source/drain region is formed in the substrate by implanting impurities of a first conductivity type proximate the plurality of interstitials. The plurality of interstitials retards diffusion of the impurities.
In accordance with another aspect of the present invention, a method of processing is provided that includes implanting a neutral ion species into a silicon-on-insulator substrate at a sub-amorphizing dosage to provide a plurality of interstitials. A source/drain region is formed in the silicon-on-insulator substrate by implanting impurities of a first conductivity type proximate the plurality of interstitials. The plurality of interstitials retards diffusion of the impurities.
In accordance with another aspect of the present invention, a method of forming a source/drain extension region in a semiconductor substrate is provided that includes implanting a neutral ion species into the substrate at a sub-amorphizing dosage to provide a plurality of interstitials and implanting impurities of a first conductivity type proximate the plurality of interstitials. The substrate is annealed to activate the implanted impurities. The plurality of interstitials retards diffusion of the implanted impurities.


REFERENCES:
patent: H986 (1991-11-01), Codella et al.
patent: 5858864 (1999-01-01), Aronowitz et al.
patent: 5970353 (1999-10-01), Sultan
patent: 6008099 (1999-12-01), Sultan et al.
patent: 6180470 (2001-01-01), Aronowitz et al.
patent: 6274450 (2001-08-01), Lin et al.
patent: 6344405 (2002-02-01), Saha
patent: 0 806 794 (1997-12-01), None
Stanley Wolf and Richard N. Tauber;Silicon Processing for the VLSI Era, vol. 1—Process Technology;pp. 297-308; 1986 (Month Unknown).

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