Semiconductor device having low on resistance high speed...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S139000, C257S140000, C257S146000, C257S147000, C257S341000

Reexamination Certificate

active

06469344

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices used as insulated gate switching devices.
BACKGROUND OF THE INVENTION
Thyristors have been used as indispensable devices for large capacity power switching owing to the low ON-state voltage characteristic. Gate Turn-Off (GTO) thyristors, for example, are widely used in these days in high-voltage large-current range applications. The GTO thyristor, however, has revealed drawbacks as follows: (1) large gate current is required for turning off the device, and (2) a large-sized snubber is needed to safely turn off the GTO thyristor. In addition, since the GTO thyristor does not show current saturation in its current-voltage characteristic, a passive component, such as a fuse, must be coupled to the thyristor so as to protect a load from short-circuiting. This greatly impedes the reduction in the size and cost of the whole system.
In 1984, MOS controlled thyristor (hereinafter abbreviated to MCT) as a voltage-driven type thyristor was proposed by Temple et al. of General Electric in IEEE IEDM Tech. Dig., pp.282 (1984). Since then, the characteristics of this type of thyristor have been analyzed and improved in various institutions worldwide. This is because the MCT, which is a voltage-drive type device, requires a far simpler gate circuit than the GTO thyristor, while assuring a relatively low ON-state voltage characteristic. The MCT, however, does not show a current saturation characteristic as in the case of the GTO thyristor, and therefore requires a passive component, such as a fuse, in practical use.
In the meantime, U.S. Pat. Nos. 4,847,671 and 4,502,070 disclose semiconductor devices having current saturation characteristics, wherein a thyristor is connected in series with MOSFET. These known devices, however, show effective saturation characteristics only where a low voltage is applied thereto, and may break down if a voltage that is equal to or higher than the breakdown voltage of the MOSFET connected in series is applied to the anode. To solve this problem, M. S. Sheker and others disclosed a dual channel type emitter switched thyristor (EST) in IEEE Electron Device Letters, vol. 12, pp.387 (1991), and proved through actual measurements that this type of device shows a current saturation characteristic even in a high voltage range. Subsequently, Iwamuro et al. presented results of their analysis on a forward bias safe operation area (FBSOA) and a reverse bias safe operation area (RBSOA) of the EST in ISPSD '93, pp.71, (1993) and ISPD '94, pp195 (1994), and paved the way to the development of voltage-driven type thyristors having safe operation areas in which the device operates safely when a load is short-circuited. Device structures similar to the EST are also disclosed in U.S. Pat. Nos. 5,381,026 and 5,464,994.
Kitagawa et al. disclosed in laid-open Japanese Patent Publication (Kokai) No. 7-50405 IEGT (Injection Enhanced Gate Transistor) that employs a gate trench structure in a voltage-driven type transistor structure, so as to achieve carrier distribution that is close to that which appears in the operation of thyristors. While the basic operation of this device is exactly the same as that of IGBT (Insulated Gate Bipolar Transistor), a portion of the surface of the device through which current passes is given a smaller area than that of IGBT, so as to raise the resistance and vary the carrier distribution inside the device to a greater extent, in particular, increase the carrier concentration at the surface of the device. To this end, the width of the trench portion may be made greater than that of the mesa portion. In the actual fabrication of such a device that has a large trench width, however, it is difficult to uniformly embed polysilicon in the inside of the trench, or the shape of the trench is undesirably changed. Thus, the current manufacturing level only permits formation of a trench having a width up to about 1.5 &mgr;m. To solve this problem, Kitagawa et al. proposed in ISPSD '95, pp.486 (1995) a device having narrow trench gate electrodes and p regions held in a floating state in terms of the potential, which are formed alternately, so as to provide the same effect as provided by the device having a large trench width. Similar devices are also disclosed by Kitagawa et al. in ISPSD '95, pp. 486 (1995), S. Eicher et al. in ISPSD '98, pp. 39 (1998), and Ogawa et al. in ISPSD '98, pp. 47 (1998).
The above-described devices are characterized by employing the thyristor structure or trench structure so that the carrier concentration is raised or increased only at the surface of the device, thereby to lower the resistance upon turn-on of the device. Upon turn-off, the carrier distribution of its portion where a depletion layer has spread out is not varied, so that the turn-off loss is reduced, thus enabling the device to achieve a high-speed characteristic equivalent to that of IGBT. Thus, the known devices attempt to lower the ON-state voltage than that of the IGBT, while achieving substantially the same turn-off speed. During the turn-off operation before the depletion layer spread out, however, the carrier concentration is high at the surface of the device as in the ON duration, and the portion of the surface of the device through which current passes is reduced, which results in a slow rate at which a large quantity of carriers present at the surface of the device are drawn away. Accordingly, the turn-off storage time is increased. In view of this situation, Kitagawa et al. proposed a trench IEGT as disclosed in laid-open Patent Publication (Kokai) No. 7-135309, wherein a hole is provided for allowing carriers to be drawn away from a p region that is in a floating state in terms of the potential, through MOSFET, so that the switching speed is increased. The structure of the trench IEGT as disclosed in laid-open Patent Publication 7-135309 will be now described in detail.
FIG. 7
is a perspective view showing cross sections of a principal part of the trench IGBT as one type of known device. In the device of
FIG. 7
, a first p base region
74
and a second p base region
75
are formed in a surface layer of an n base region
73
, and a plurality of n source regions
76
are formed in a surface layer of the first p base region
74
such that the regions
76
are spaced apart from each other. A trench is formed which extends from the surface of the device to a certain depth, and a gate electrode
78
is formed in the trench with a gate insulating film
77
interposed between the gate electrode
78
and the inner wall of the trench.
A cathode electrode
82
is formed on the surface of the first p base region
74
and the n source regions
76
. The second p base region
75
extends continuously in the Z-axis direction, until one end of the region
75
reaches an n base region
87
as part of the n base region
73
. Also, a p
+
region
88
is formed outwardly of the n base region
87
. The p
+
region
88
is connected to the first p base region
74
. It is to be understood that the n base region
87
is a portion of the n base region
73
that is interposed between the second p base region
75
and the p
+
region
88
.
The trench extends in the Z-axis direction until it reaches the p
+
region
88
, and the cathode electrode
82
is formed on the surface of the p
+
region
88
. A p emitter region
71
is formed on the rear surface of the n base region
73
, and an anode electrode
83
is formed on the surface of the p emitter region
71
. The anode electrode
83
, cathode electrode
82
, and the gate electrode
78
are connected to an anode terminal A, cathode terminal K and a gate terminal G, respectively. It is to be noted that the n source region
76
, p emitter region
71
, cathode electrode
82
, anode electrode
83
, cathode terminal K and the anode terminal A respectively correspond to an n emitter region, p collector region, emitter electrode E, collector electrode C, emitter terminal E and a collector terminal C, which will b

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