Logic circuit with output high voltage boost and method of...

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Bipolar transistor

Reexamination Certificate

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C327S065000, C327S089000

Reexamination Certificate

active

06411129

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates, in general, to logic gates and, more particularly, to differential logic gates with improved output logic drive.
BACKGROUND OF THE INVENTION
Differential logic gates have a wide range of applications. Clock generation circuits, for example, provide an excellent application for which differential logic gates can be used. Clock generation circuits implemented with differential logic gates have the capability of significantly reducing the clock skew and jitter over an equivalent design implemented with single-ended logic families. In fact, applications requiring superior noise immunity are especially suited for differential logic implementations. Differential inputs used in differential logic families promote common mode rejection of cross talk noise and EMI radiation.
Semiconductor process improvements tend to shrink the geometric dimensions of semiconductor devices. Speed and power consumption are two examples of motivations for performance enhancements. As newer generations of superior semiconductor devices are manufactured, it is advantageous to replace older logic families with the newer logic generations, which do not dissipate as much energy as the older logic families and yet demonstrate superior speed performance. One problem, however, induced by transplanting the newer logic families into applications utilizing older logic families, is the reduction in current conduction capability of the newer logic families due to increased current densities. As the current density increases, the base-emitter voltage, V
be
, of the newer devices also increase, creating a larger voltage drop across emitter follower output drivers.
Referring to
FIG. 1
, an enhanced output drive, differential logic circuit
10
is illustrated. Transistor
24
is an emitter follower output driver receiving base current drive from p-type, Metal Oxide Semiconductor (PMOS) device
16
. Transistors
18
and
20
form the typical differential logic input, which receive complimentary input logic levels. A logic high voltage at the IN terminal causes transistor
18
to transition to an on, or non-conductive, state which brings the gate terminal of inverting PMOS transistor
16
to a logic low potential. Transistor
16
begins to conduct current, since the base terminal of transistor
24
is substantially equal to V
cc
. Transistor
16
supplies base current drive to the base terminal of transistor
24
only when transistor
20
is in a non-conductive state. In the absence of PMOS transistor
16
, the required base current drive would be derived from resistor
14
operating from top rail supply potential V
cc
. The resulting output logic high voltage, V
OH
, would be V
OH
=V
CC
−V
14
−V
be-24
, where V
14
is the voltage drop across resistor
14
and V
be-24
is the base-emitter voltage drop across transistor
24
. As the logic at terminal IN inverts to a logic low, PMOS transistor
16
turns off, or transitions to a non-conductive state, thereby canceling base current drive into transistor
24
. An inherent speed problem exists with differential logic circuit
10
, such that PMOS transistor
16
switches on and off depending on the logic state at terminal IN. PMOS transistor switches on during a V
OH
output condition and switches off during a low output voltage V
OL
condition. Differential logic circuit
10
also introduces the need to mix MOS technology with bipolar technology, which complicates the semiconductor process and drives the manufacturing costs upward.
A need exists, therefore, for a differential logic gate, which provides improved output logic drive, at faster speeds with reduced manufacturing complexity.


REFERENCES:
patent: 5023479 (1991-06-01), Jeffery et al.
patent: 5124580 (1992-06-01), Matthews et al.
patent: 5485110 (1996-01-01), Jones et al.
patent: 5606272 (1997-02-01), Behbahani et al.
patent: 6265901 (2001-07-01), Stern et al.
patent: 6292031 (2001-09-01), Thompson et al.
patent: 5-343981 (1993-12-01), None

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