Semiconductor memory with voids for suppressing crystal defects

Details Semiconductor memory with voids for suppressing crystal defects Semiconductor memory with voids for suppressing crystal defects

2001-02-02

2002-10-22

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S201000, C438S216000, C438S257000

Reexamination Certificate

active

06469339

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly a semiconductor device which can suppress occurrence of crystal defects in a semiconductor substrate during and after manufacturing of the semiconductor device.
2. Description of the Background Art
In recent years, a flash memory which is a kind of nonvolatile semiconductor memory device has been expected as a useful memory device for the next generation because it can be manufactured at a lower cost than a Dynamic Random Access Memory (DRAM). A memory cell of a flash memory includes a source region connected to a corresponding source line, a drain region connected to a corresponding bit line, a floating gate electrode for storing information and a control gate electrode connected to a corresponding word line.
An FN (Fowler Nordheim) current phenomenon, a channel hot electron phenomenon or the like is caused in a gate insulating film formed of a tunnel oxide film, which is located immediately under the floating gate electrode, for injecting electrons into the floating gate electrode or removing electrons accumulated in the floating gate electrode so that erasing or writing of information is performed. As a result of the foregoing injection and removal of electrons with respect to the floating gate electrode, a binary state of the threshold is determined according to the state of electrons in the floating gate electrode, and “0” or “1” is read out depending on this binary state.
A memory cell array structure of an NOR (Not OR) type is used most generally in a nonvolatile semiconductor memory of a floating gate type such as a flash memory of the foregoing structure and other EEPROMs (Electrically Erasable and Programmable Read Only Memories) including floating gate electrodes.
The NOR type array is provided with contacts, which are connected to drain regions of memory cells in respective rows. Bit lines are formed in the row direction. Each bit line is formed of, e.g., an interconnection of a policide structure of metal silicide and polycrystalline silicon or a metal interconnection. Gate interconnections of memory cells in respective columns are formed in the column direction. The bit lines and columns lines are arranged in a matrix form.
An example of a planar structure of conventional flash memories is shown in FIG.
43
. As shown in
FIG. 43
, control gate electrodes
112
a,
112
b,
112
c
and
112
d
which are spaced from each other extend across a plurality of element formation regions S, which are isolated from each other by trench isolating oxide films
103
. Floating gate electrodes
110
a,
110
b,
110
c
and
110
d,
which are located immediately under control gate electrodes
112
a,
112
b,
112
c
and
112
d,
are formed in portions where these control gate electrodes cross element formation regions S, respectively.
A source regions
106
a
is formed, e.g., in one of element formation regions S located on the opposite sides of control gate electrode
112
b,
and a drain region
104
b
is formed in the other element formation region S. Each drain region is electrically connected to the bit line (not shown) via a contact hole
117
.
The source regions are electrically connected together by an impurity region of a predetermined conductivity type, which is formed in a silicon substrate portion located immediately under a region between control gate electrodes
112
a
and
112
b.
The above source region structure in the memory cells is particularly referred to as a self-align source structure. In the self-align source structure, the source regions of the respective memory cells are not connected by an interconnection via a contact, but are connected by a diffusion layer interconnection. In other words, the diffusion layer interconnection includes the source regions.
A method of manufacturing a self-align source structure will now be described. A photoresist pattern (not shown) is formed over an entire area except for the region defined between control gate electrodes
112
a
and
112
b
shown in FIG.
43
and others, where the source regions are to be formed, respectively.
Using the photoresist pattern and control gate electrodes
112
a
and
112
b
as a mask, etching is effected to remove trench isolating oxide films
103
located in the region between control gate electrodes
112
a
and
112
b
so that the surfaces of silicon substrate located immediately under trench isolating oxide films
103
are exposed.
Then, ions of a predetermined conductivity type are implanted into the exposed surfaces of silicon substrate located between control gate electrodes
112
a
and
112
b
so that the respective source regions are formed, and the diffusion layer interconnection connecting the respective source regions in the column direction is formed in a self-aligned fashion.
Thereby, a sectional structure shown in
FIG. 44
is formed. In
FIG. 44
, which is a cross section taken along section line XLIV—XLIV in
FIG. 43
, a diffusion layer interconnection
106
including the source regions is formed in a self-aligned fashion at the surface of silicon substrate
102
, which includes the surfaces of grooves
102
a,
and is exposed by removal of trench isolating oxide films
103
. This diffusion layer interconnection
106
forms the source region in a portion (i.e., a region between grooves
102
a
) of the main surface of silicon substrate
102
.
In a sectional structure shown in
FIG. 45
, which is a cross section taken along line XLV—XLV in
FIG. 45
, trench isolating oxide films
103
are removed from the region between control gate electrodes
112
a
and
112
b
as well as the region between control gate electrodes
112
c
and
112
d
so that openings
103
exposing the surface of silicon substrate
102
(bottoms of grooves
102
a
) are formed. Diffusion layer interconnections
106
including source regions are formed at the exposed surface portions of silicon substrate
102
.
Thereafter, sidewall insulating films
114
a
are formed on side surfaces of control gate electrodes
112
a-
112
d
including the side surfaces of openings
103
a,
as shown in
FIGS. 44 and 45
. Then, a TEOS (Tetra Ethyl Ortho Silicate glass) film
115
covering control gate electrodes
112
a
-
112
d
is formed.
Then, as shown in
FIGS. 46 and 47
, a BPTEOS (Boro Phospho Tetra Ethyl Ortho Silicate glass) film
116
which will form an interlayer insulating film is then formed on TEOS film
115
. Then, as shown in
FIGS. 48 and 49
, thermal processing or polishing is effected to smoothen the surface of BPTEOS film
116
. In these manners, a major portion of the flash memory of the NOR type array is completed.
According to this flash memory, the self-align source structure is employed in the source region of memory cell so that it is not necessary to make an electrical connection between the source regions via contacts. Thus, the source region of memory cell is formed in the region defined between the neighboring two control gate electrodes according to design rules, and therefore the memory cells can be miniaturized and/or can be arranged at high density.
According to the flash memory employing the self-align source structure, as described above, the source region is formed in the region defined between the neighboring two control gate electrodes according to the minimum design rule so that the memory cells can be miniaturized.
Further, the trench isolating structure which uses trench isolating oxide film
103
is used as the isolating structure for electrically isolating the elements, as described above. This trench isolation structure allows further miniaturization compared with a conventional LOCOS isolation structure. In the trench isolation structure, groove
102
a
having relatively steep side surfaces is formed in silicon substrate
102
, and is filled with the oxide film to form trench isolating oxide film
103
, as shown in FIG.
44
.
However, when forming the source region of the self-aligned structure in the flash memory described above, trench isolating oxide film
103

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